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The first multi-layer stacked 3D Flash memory was proposed as BiCS FLASH in 2007 [1]. Since then, memory bit density has grown rapidly due to the increase in the number of stacked layers from continuous 3D technology innovations. On the other hand, the multi-level-cell technology, which was initially proposed for 2D Flash, has also been adopted to 3D Flash memories. The first 3b/cell 32-layer Flash was presented in 2015 [2], followed by a 48-layer one in 2016 [3], and a 64-layer one in 2017 [4,5]. This paper describes a 512Gb 3b/cell 3D Flash memory in a 96-word-line-layer BiCS FLASH technology. This work implements three key technologies to improve performance: (1) a string based start bias control scheme achieves a 7% shorter program time; (2) a smart V t -tracking read improves read retry performance by minimizing the tracking time and supporting a program suspend read function, and; (3) a low-pre-charge sense-amplifier bus scheme reduces both the power consumption and the data-transfer time between the sense amplifier (SA) and the data cache by half. Figure 20.1.1 shows the die micrograph and the summary of the key features of the chip.

A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm2, has been successfully developed. This is the world's first integrated semiconductor chip fabricated with 56-nm CMOS technologies. The effective cell size including the select transistors is 0.0075 mum2 per bit, which is the smallest ever reported. To decrease the chip size, a very efficient floor plan with one-sided row decoder, one-sided page buffer, and one-sided pad is introduced. As a result, an excellent 70% cell area efficiency is realized. The program throughput is drastically improved to twice as large as previously reported and comparable to binary memories. The best ever 10-MB/s programming is realized by increasing the page size from 4kB to 8kB. In addition, noise cancellation circuits and the dual VDD-line scheme realize both a small die size and a fast programming. An external page copy achieves a fast 93-ms block copy, efficiently using a 1-MB block size

NAND flash memory use in digital still cameras and cellular phones is driving demand for larger-capacity storage. Moreover, NAND flash has the potential to replace HDDs. To achieve larger capacity while maintaining low cost per bit, technical improvements in feature size and area reduction are essential. To meet the stringent requirements, we develop a 16 Gb 4-level NAND flash memory in 43 nm CMOS technology. In 43 nm generation, gate-induced drain leakage (GIDL) influences the electrical field on both sides of NAND strings. GIDL causes severe program disturb problems to NAND flash memories. To avoid GIDL, two dummy wordlines (WL) on both sides of NAND strings are added. This is effective because the dummy gate voltages, are selected independent of the program inhibit voltage.

Fabricated in 56nm CMOS technology, an 8Gb multi-level NAND Flash memory occupies 98.8mm2, with a memory cell size of 0.0075mum/b. The 10MB/s programming and 93ms block copy are also realized by introducing 8kB page, noise-cancellation circuits, external page copy and the dual VDD scheme enabling efficient use of 1MB blocks

Three types of zinc complexes, chlorotris[2(1H)-pyridinethionato]dizinc (3), dichlorotetrakis[2(1H)-pyridinethionato]trizinc (4), and chloro[2(1H)-pyridinethionato]zinc (5) were produced by the reactions of bis[2(1H)-pyridinethionato]zinc (2) and zinc chloride. The product in the reactions varies depending on the solvent. The mutual transformation reactions among 3, 4, 5, 2, and oxohexakis[2(1H)-pyridinethionato]tetrazinc were described. The formations of 5, 4, and 3 were explained by stepwise additions of 2 to zinc chloride based upon a view that these complexes are the adducts of 2 with zinc chloride in molar ratios of 1 : 1,2 : 1, and 3 : 1. Analogously, the correlation of the known polynuclear zinc complexes was systematically rationalized by stepwise additions of L2Zn (L=ligand) to ZnX2 (X=Cl or OH) or ZnO.