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A 28 GHz watt-level CMOS SPDT switch with integrated electro-static discharge protection is designed and fabricated in a 65 nm CMOS process for a fifth-generation mobile communication. The measured insertion losses of the SPDT are 2.2 dB and 2.6 dB for transmit and receive modes, respectively. The fabricated SPDT switch shows output P1dB of >30 dBm for transmit mode and input P1dB of 4.3 dBm for receive mode.

The effects of non-idealities including clock jitter, rise/fall-time mismatch of a pulse, and pulse-amplitude-level non-linearity on conventional delta-sigma-only and Manchester/delta-sigma-modulated microwave signals are studied. According to the experimental and simulation results, the Manchester/delta-sigma scheme is more vulnerable to jitter than the conventional delta-sigma scheme due to the higher number of pulse transitions by Manchester codes. It is found that, however, because of the repetitive (or multi-pulse) nature, the Manchester/delta-sigma system shows better signal quality performance against a rise and fall time asymmetry. This is mainly because the Manchester pulse waveform is more similar to a return-to-zero format where every encoded bit has both rising and falling edges and is therefore immune to the waveform asymmetry.

This paper presents a miniaturized 28-GHz FEM implemented in 0.15-µm InGaAs/GaAs E-mode pHEMT process. It is designed for use with 28-GHz switching beamforming systems. In order to miniaturize the system, the RF FEM is mounted on the printed circuit board in the form of individual PA, switch, and LNA chips, and development has been made to facilitate the mounting of mobile terminals. The results of the FEM transmitter verification including the implemented filter on the PCB have a gain of 17.9 dB, an output P1 dB of 24.2 dBm and an EVM of -30 dB at 20 dBm output. As a result of the receiver verification, the gain is around 20 dB, the input P1 dB is -30 dBm, and the EVM performance of -30 dB is tested at -10 dBm output.

In this paper, we propose a low noise amplifier (LNA) using a g m -boosting technique with improved stability using transformers in the millimeter-wave (mm-Wave) band. The transformer composed of three inductors improves not only stability, but also gain and low-noise performance of the LNA. The conditions for stability shows that the proposed structure can guarantee good stability over a high frequency range. The chip was fabricated using the TSMC 65-nm CMOS process and it has an active chip area of 0.11 µm2. The fabricated LNA has a gain of 18.33 dB and a noise figure (NF) of 3.25–4.2 dB. The stability factor µ values are 9.7 and 5.2 at the source and load sides of the LNA, respectively. The 3-dB bandwidth of the LNA is 24.9–32.5 GHz and the chip consumes 17.1-mA current from a 1.2-V supply.

A 1.8V MIPI RF front-end (RFFE) circuit for a slave with a 1.0V supply is designed using a CMOS 65 nm process as a control block for a millimeter-wave beamforming array. It is consisted of a MIPI RFFE slave logic, power-on-reset (PoR), SCLK receiver, and SDATA transceiver to support the MIPI RFFE master-slave interface with MIPI RFFE bus. According to simulation results, the designed MIPI RFFE interface circuit provides rise and fall time of less than 3.3 ns with a 26 pF load (one master-eight slave configuration) at the transmission rate of 26 MHz, satisfying the requirement of 6.5 ns in the MIPI RFFE specification version 1.10.

This paper presents a 6-bit 28GHz phase shifter in 65nm CMOS technology. The phase shifter is composed of switching-type phase shifters to achieve low power consumption, low insertion loss, and bidirectionality. The relative phase shift varies from 0° to 354.375° with a step of 5.625°. The result of EM simulation shows that the phase shifter has the insertion loss less than 8.63dB over a frequency range of the 26.5 to 29.5GHz. The return loss is smaller than −10.5dB and the RMS phase error is 3.11°. The core size of the phase shifter is $\mathbf{0.38 \times 0.98 mm^2}$

28 GHz SPDT switch has been designed and fabricated in 65 nm CMOS with deep N-well as a building block for beamforming-based 5th generation mobile communication systems. The measured insertion loss is 1.8 dB at 28 GHz, and IIP3 is measured as 11.75 dBm. The input and output return losses are $ and $ , respectively.

A K-band CMOS ultra-wideband (UWB) four-channel radar front-end based on timed-array coherent pulsed oscillators is presented. The trigger-signal delay method of the oscillator array with an additional 1-bit RF phase shifter is proposed to achieve beam-forming with wide angular coverage and high angular resolution. The phase coherency of the K-band UWB signal is achieved by using an asymmetric control of the pulsed oscillator. This allows it to detect the direction of a target as well as the accurate distance using a single antenna per channel. The chip is fabricated with ${\hbox{0.13-}}\mu{\hbox{m}}$ CMOS technology and the chip size is 3.9 mm by 1.7 mm. The output spectrum is centered on 26.0 GHz and satisfies the Federal Communications Commission spectral mask. The system attains the angular resolution of 9 $^{\circ}$ in the range from $-{\hbox{45}}^{\circ}$ to $+{\hbox{45}}^{\circ}$ . Total power consumption is only $\sim {\hbox{68 mW}}$ , mainly used in the receiver and digital blocks.

We propose a millimeter-wave (mm-wave) InGaAs enhancement-mode (E-mode) 0.15-um pHEMT low-noise amplifier (LNA). The LNA achieves 21.9-dB gain with simulation results of 2.19-dB noise figure (NF) and 9.9-dBm P1dB using 3-V power supply as it consumes 9 mA. The bandwidth of the LNA is 17 GHz (from 18.9 GHz to 35.9 GHz) and the fractional bandwidth (FBW) is 62 %.

We present a 28-GHz low-noise amplifier (LNA) using 0.15-um InGaAs pHEMT enhancement-mode (E-mode) technology. The 28-GHz LNA exhibits a gain of 22.2 dB and a 3-dB bandwidth of 14.1 GHz (22.7–36.8 GHz) under 3-V supply with 38.5-mA current consumption. The simulation results of the LNA show a noise figure (NF) of 2.13 dB and a P1dB of 10.8 dBm. The chip size is 1488 um × 796 um.

We present a synchronization method and coherent ultra-wideband transceivers for a widely separated multiple-input multiple-output (MIMO) radar. Synchronization is essential for MIMO operation, but a spatially spread radar array is not a good structure for it. A wireless cooperative synchronization method is based on coherency of pulse signals and highly accurate delay estimation and they are implemented through a coherent pulse generator and a fine delay-based receiver. Distance measurements of a radar transceiver (TRX) show that the maximum mean error is 4 mm for the target in a range of 0.2 m-8.0 m. Synchronization measurements of two radar TRXs show that the maximum mean error of the asynchronous time difference is 11 ps for the target in a range of 0.25-8.0 m. 2-D images for multiple targets and fluctuational radar cross sections are achieved with the proposed synchronization method under MIMO operation.

A low-noise ultrawideband CMOS mixer circuit for the down conversion of a K-band signal is presented. A bleeding path gm-boosting technique is proposed, which reduces the effect of noise sources of the proposed mixer. The measurement results show that the minimum noise figure is 3.61 dB at 24 GHz when consuming 2.6 mW at a 1.5-V supply voltage. The results also show a conversion gain of 9.15 dB, a of P1dB of -13 dBm, and an isolation of a local oscillator port to a radio frequency port of -40 dB. The circuit was fabricated using 0.13-μm CMOS technology with a chip area of 0.68 x 1.07 mm2.

A low-power 50-GHz LC-VCO has been presented. Throughout EM analysis, an inductor having a quality factor of 14.3 was implemented with a microstrip line. The analyzed characteristics of a MOS varactor limit the LC tank performance due to its low quality factor. In order to overcome the LC tank performance and operate at low-power consumption, the negative transconductance stage was evaluated in various ways and found at the condition of the optimized MOSFET size and bias point. The proposed VCO was implemented in a 65-nm CMOS technology. The measurement results show a frequency range of 48.61 GHz ∼ 50.84 GHz and an output power of −10 dBm. The required VCO current is about 4.7 mA from a 0.7 V supply.

This paper presents a low power UWB radar transceiver IC, which is used to make a radar system with precise range accuracy. The range accuracy is allowed by a variable delay circuit which can control the delay by 5 ps resolution. The detecting range of the transceiver is from 0.15 m to 8.4 m. The measurement results show that the maximum error is 3.75 mm. The circuit is implemented in a 0.13 µm CMOS process with the die area of 1.28 × 1.07 mm2. The total power consumption of the core circuit is 6.89 mA with the supply voltage of 1.5 V.