197 results on '"Sunil R. Das"'
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2. An Optimized Tongue Drive System for Disabled Persons.
3. Face Identification Based on Discrete Wavelet Transform and Neural Networks.
4. Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation.
5. Short duration voice data speaker recognition system using novel fuzzy vector quantization algorithm.
6. A compact multispectral image capture unit for deployment on drones.
7. An algorithm for generating prime implicants.
8. Image processing based system for classification of vehicles for parking purposes.
9. Designing elementary-tree space compressors using AND/NAND and XOR/XNOR combinations.
10. Design and implementation of high-performance master/slave memory controller with microcontroller bus architecture.
11. Compressed video watermarking technique.
12. Data compression using mixed cascade of nonlinear logic.
13. Aliasing-Free Space Compaction in VLSI with Cascade of Two-Input OR/NOR Logic.
14. On System-on-Chip Testing Using Hybrid Test Vector Compression.
15. A Novel Technique for Input Vector Compression in System-on-Chip Testing.
16. Implementation of Embedded Cores-Based Digital Devices in JBits Java Simulation Environment.
17. Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits.
18. JBits Implementation and Design Verification in Space Compressor Design of Digital Circuits.
19. Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability.
20. An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers.
21. A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers.
22. Real Time Intelligent Traffic Light System
23. Pseudorandom encoding for structured light applications.
24. Aliasing-free compaction revisited.
25. On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing.
26. Delay Fault Coverage Enhancement Using Multiple Test Observation Times.
27. Testing Analog and Mixed-Signal Circuits With Built-In Hardware - A New Approach.
28. Space compactor design in VLSI circuits based on graph theoretic concepts.
29. Crosstalk test pattern generation for dynamic programmable logic arrays.
30. An improved output compaction technique for built-in self-test in VLSI circuits.
31. A built-in self-testing method for embedded multiport memory arrays.
32. Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization.
33. Fault simulation and response compaction in full scan circuits using HOPE.
34. An adaptive compressed MPEG-2 video watermarking scheme.
35. Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware.
36. Measuring availability indexes with small samples for component and network reliability using the Sahinoglu-Libby probability model.
37. On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition.
38. Designing General-Purpose Fault-Tolerant Distributed Systems - A Layered Approach.
39. Aliasing-Free Compaction in Testing Cores-Based System-on-Chip (SoC) using Compatibility of Response Data outputs.
40. Robotic tactile recognition of pseudorandom encoded objects.
41. A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays.
42. CACOP - A Random Pattern Testability Analyzer.
43. Instrumentation applications of multibit random-data representation.
44. An efficient BIST method for non-traditional faults of embedded memory arrays.
45. Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets.
46. Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering.
47. Random Pattern Testability Enhancement by Circuit Rewiring.
48. Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis.
49. An adaptive path selection method for delay testing.
50. Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities.
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