464 results on '"Sunil P. Khatri"'
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2. An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency.
3. A Mixed-Signal Quantized Neural Network Accelerator Using Flash Transistors.
4. Scaled Population Division for Approximate Computing.
5. An Extremely Low-voltage Floating Gate Artificial Neuron.
6. A Hardware Validation Framework for a Networked Dynamic Multi-factor Security Protocol.
7. A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator.
8. A Digital Low Dropout (LDO) Voltage Regulator Using Pseudoflash Transistors.
9. TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations.
10. A Flash-based Digital to Analog Converter for Low Power Applications.
11. A Flash-based Current-mode IC to Realize Quantized Neural Networks.
12. A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells.
13. NIST-Lite: Randomness Testing of RNGs on an Energy-Constrained Platform.
14. CIDAN: Computing in DRAM with Artificial Neurons.
15. A Mathematical Framework for Exploring Protein Folding Dynamics using Probabilistic Model Checking.
16. Scaled Population Subtraction for Approximate Computing.
17. A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells.
18. Scaled Population Arithmetic for Efficient Stochastic Computing.
19. A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron.
20. Hardware Acceleration of Hash Operations in Modern Microprocessors.
21. Threshold Logic in a Flash.
22. A Homomorphic Encryption Scheme Based on Affine Transforms.
23. A Plain-Text Incremental Compression (PIC) Technique with Fast Lookup Ability.
24. Synchronization of Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications.
25. A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells.
26. Fast, Ring-Based Design of 3-D Stacked DRAM.
27. A Robust C-element Design with Enhanced Metastability Performance.
28. Design of a Flash-based Circuit for Multi-valued Logic.
29. Circuit Level Design of a Hardware Hash Unit for use in Modern Microprocessors.
30. Fast, Ring-Based Design of 3D Stacked DRAM.
31. An FPGA-Based Coprocessor for Hash Unit Acceleration.
32. Fast and Highly Scalable Bayesian MDP on a GPU Platform.
33. A GPU-CPU heterogeneous algorithm for NGS read alignment.
34. Comparing Leakage Reduction Techniques for an Asynchronous Network-on-Chip Router.
35. A GPU-based implementation of a sensor tasking methodology.
36. A practical methodology to validate the statistical behavior of bloom filters.
37. Implementing low power digital circuits using flash devices.
38. A novel hardware hash unit design for modern microprocessors.
39. Exploring static and dynamic flash-based FPGA design topologies.
40. GPU acceleration for Bayesian control of Markovian genetic regulatory networks.
41. A Ternary-Valued, Floating Gate Transistor-Based Circuit Design Approach.
42. A Survey of Software and Hardware Approaches to Performing Read Alignment in Next Generation Sequencing.
43. Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs.
44. An Efficient Approach to Sample On-Chip Power Supplies.
45. Exploring the viability of stochastic computing.
46. FTCAM: An Area-Efficient Flash-Based Ternary CAM Design.
47. A comparison of FinFET based FPGA LUT designs.
48. Look-up Table Design for Deep Sub-threshold through Full-Supply Operation.
49. An area-efficient Ternary CAM design using floating gate transistors.
50. An asynchronous Network-on-Chip router with low standby power.
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