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Abstract Due to scarcity of anomaly situations in the early manufacturing stage, an unsupervised anomaly detection (UAD) approach is widely adopted which only uses normal samples for training. This approach is based on the assumption that the trained UAD model will accurately reconstruct normal patterns but struggles with unseen anomalies. To enhance the UAD performance, reconstruction-by-inpainting based methods have recently been investigated, especially on the masking strategy of suspected defective regions. However, there are still issues to overcome: (1) time-consuming inference due to multiple masking, (2) output inconsistency by random masking, and (3) inaccurate reconstruction of normal patterns for large masked areas. Motivated by this, this study proposes a novel reconstruction-by-inpainting method, dubbed Excision And Recovery (EAR), that features single deterministic masking based on the ImageNet pre-trained DINO-ViT and visual obfuscation for hint-providing. Experimental results on the MVTec AD dataset show that deterministic masking by pre-trained attention effectively cuts out suspected defective regions and resolves the aforementioned issues 1 and 2. Also, hint-providing by mosaicing proves to enhance the performance than emptying those regions by binary masking, thereby overcomes issue 3. The proposed approach achieves a high performance without any change of the model structure. Promising results are shown through laboratory tests with public industrial datasets. To suggest EAR be possibly adopted in various industries as a practically deployable solution, future steps include evaluating its applicability in relevant manufacturing environments.

Scan chains are essential for enhancing the testability of semiconductor circuits. While scan chains enhance the testing capability, defects can also occur in scan chains due to the hardware overhead caused by scan chains. To prevent a decrease in yield due to such defects, scan chain diagnosis is widely used in semiconductor manufacturing as an important system. Particularly, with the increasing complexity of semiconductor circuits, there is a growing necessity for the diagnosis of intermittent faults. Since the distinct patterns are shown in test results for intermittent faults compared to permanent faults, a decrease in diagnostic accuracy is caused by the occurrence of intermittent faults. To address this problem, this paper introduces a new deep-learning-based scan-chain diagnosis method, designed to diagnose both intermittent and permanent faults. The proposed method introduces two new concepts for diagnosing not only permanent but also intermittent faults. One is a CNN optimized for scan chain diagnosis, and the other is newly optimized input data tailored for this CNN architecture. The proposed CNN architecture is composed of multiple layers centered around the modified inception module adapted for scan chain diagnosis, maintaining spatial and local information while enabling additional feature extraction. Furthermore, the new input data is multi-channel data composed of subset failure vectors (SFVs), integer failure vectors (IFVs), and fan-out vectors, allowing for the maximization of CNN characteristics. The experimental results demonstrate that diagnostic accuracy for intermittent faults is significantly improved by the proposed method compared to previous works.

Abstract Agricultural sensors are powerful tools to optimize crop productivity while conserving natural resources. Here we report a crop water-stress detector based on a plasmonically-enhanced micromechanical photoswitch capable of detecting water content in leaves that is lower than a predetermined threshold without consuming electrical power when the leaf is healthy. The detection mechanism exploits the energy in a specific narrow-spectral band of solar radiation reflected off leaves that is strongly correlated to the water content in plants. This biosensor relies on a spectrally selective infrared plasmonic absorber and a thermally sensitive micro-cantilever to harvest the reflected solar energy and further produce a digitized wakeup-bit only when the monitored leaf is water-stressed. In particular, we demonstrate that the detector activates a commercial water pump when a soybean plant is water-stressed. The 10-year battery lifetime of the proposed detector pave the way for the development of high-granularity, maintenance-free sensor networks for large-scale smart-farms.

As the technology node of the dynamic random-access memory (DRAM) continues to decrease below the 10-nm-class, bit-cell failures due to the external environments have increased. As a result, DRAM vendors perform post package inspections to provide fault-free DRAMs to the end customers. However, post package inspections require considerable test costs. To overcome this issue, an in-DRAM built-in self-test (BIST) mechanism is implemented in this study as an alternative solution. Herein, we propose compact and high test-coverage features for the in-DRAM BIST that to resolve the area problem when applied to a commodity DRAM. The proposed BIST secures the same test coverage with a shorter time than the conventional BIST. The proposed BIST reduces the test time by 52% of the DDR BIST in functions with the same test coverages. Further, the implemented BIST can achieved an area overhead of 0.051% based on a 16Gb DDR4 DRAM in the second generation of the 10-nm-class DRAM process.

Post-silicon debug has become important with the increased complexity of circuit designs. However, the increase in debug resource costs owing to improved observability has posed a major challenge. To overcome this challenge, this study proposes on-chip error detection that reuses built-in self-repair (BISR). The proposed method utilizes the components of BISR as storages of golden signatures and comparators for error detection. Also, it detects error-suspect cycles more precisely by using parent and child multiple-input signature registers (MISRs). In addition, it provides selective capture and store methods that selectively capture error-suspect debug data in buffers and store them in the DRAM, respectively. The experimental results of various debug cases demonstrate that the proposed method significantly reduces the buffer size, DRAM usage, and debug time compared to previous methods.

The memory cell density and memory capacity have been increased for obtaining larger and faster memory. However, this threatens the memory reliability by increasing the probability of faulty cell generation. In this paper, a fast and small-area built-in redundancy analysis (RA) for the post-bond repair process in 3D memory is proposed. Spare line allocation is the structure for memory repair which the most widely used. However, the spare line structure that replaces the entire line which contains faults in each memory layer occurs inefficiency in repairing a small number of faults, including single faults, and it is difficult to share spares between layers. The proposed idea is to use spare line to repair line faults according to the characteristics of it, and to complement the structural limitations by proposing a new redundant spare. This is base common spare located on the base die, and it can be shared across all layers. The proposed BIRA improves the efficiency of spare lines with two complementary spare resource structures, achieving a short repair time and high repair rate. The proposed BIRA achieves 100% repair rate when there are at least 2 times more faults than the previous works with the same hardware overhead. In addition, it takes only at most 80% of the analysis time compared to the previous works, and as the number of faults increases, the analysis time reduction becomes greater compared to the previous works.

Scan-based Design for Testability (DFT) is widely used in industry as it consistently provides high fault coverage. However, scan-based DFT is prone to security vulnerabilities where attackers use the scan design to obtain secret information from the system-on-chip. Existing countermeasures for such attacks contribute to enhancing the security of the scan design but cannot prevent the loss of debuggability because scan dumps are also treated as a type of attack even though they provide debuggers with high observability after a chip has been packaged. Therefore, it is necessary for secure scan architectures to effectively defend various existing attacks without losing the debuggability of the scan dump. In this paper, we propose a secure scan architecture using a skew-based lock and key to enhance the security of the scan design while maintaining the debuggability of the scan dump. The proposed architecture builds up an invisible barrier against the attacker by combining the physical information into a lock and key scheme. While the security is improved effectively with the new barrier by only a few key flip-flops, the scan dump, which has been treated as an attack, is protected separately in the acquisition and analysis steps using secure software in the proposed architecture. Performance evaluations show that the area and the test time overhead in the proposed architecture are negligible while achieving both a high level of security and scan dump protection.

Scan-based logic built-in self-test (LBIST) is widely used for supporting the in-system test in automotive systems. Although this technology has the advantage of low-cost testing, it suffers from low fault coverage and high switching activity during the test. This can lead to many undetected defects, excessive heat dissipation, and IR drop, inducing catastrophic risks to functional safety. Therefore, improving these two key factors is crucial to alleviate reliability problems in the automotive domain. Most previous works have focused on controlling the enormous toggling level of random patterns; however, one of the main disadvantages of these approaches is low fault coverage. Unfortunately, additional hardware costs associated with memory elements or test points are required for detecting the remaining faults. We propose a novel LBIST scheme based on weight-aware scan grouping and scheduling (WGS) to overcome these difficulties. Since the required test time of each automotive product is limited, the proposed scheme freezes the test time and focuses on improving both aforementioned factors significantly. Our approach divides scan cells into two categories: the coverage-efficient scan group and power-efficient scan group, and then it conducts weight-based scan cell reordering. Biased random patterns are fed to enhance fault coverage for the first category. For the second category, scheduling and disabling are performed to reduce switching activity. Finally, physical-aware reordering based on an inverter is performed to reduce routing overhead. Experimental results demonstrate the feasibility of the WGS methodology on the ITC’99 and OpenRISC benchmark circuits.

Scan chain diagnosis is essential to solving yield-reduction problem caused by the miniaturization of manufacturing process. The accurate diagnosis of scan chain faults that frequently occur in the initial process is vital for rapidly improving yield. Moreover, the importance of scan chain diagnosis with a high resolution for the multiple faults is increasing because multiple faults occur in the early stages of the process, further increasing the cost of physical failure analysis. Although multiple faults can be diagnosed with existing methods, a high diagnostic resolution is difficult to achieve in the early stages of the process (where many faults occur) due to the rapid increase in the number of diagnosed fault candidates as the number of actual faults in the circuit increases. In this paper, a novel reconfigurable scan architecture that reconfigures the diagnosis paths and a test algorithm that uses this scan architecture are proposed to reduce the number of diagnosed fault candidates in the scan chain diagnosis with multiple circuit faults. Experimental results indicate that the proposed method achieves the higher diagnostic resolution for multiple faults than conventional methods. In addition, the proposed method reduces the routing overhead by scan partitioning.

Advanced capacity and density of memory have resulted in an increase in the probability of memory faults. The in-memory Error Correction Code (ECC), which solves this problem, is a widely used technology to improve the yield of highly integrated memory. However, the use of in-memory ECC causes problems that have not been considered in memory repair algorithms. Redundancy analysis is effective for repairing memory with redundant memory and in-memory ECC. In this paper, an ECC-aware fast and reliable pattern matching redundancy analysis algorithm for memory using both spare memory and in-memory ECC is proposed. This algorithm simplifies large-scale fault groups using in-memory ECC and includes an early termination method that can determine whether a memory that cannot be repaired with line spares can be repaired considering in-memory ECC. Experimental results show that the proposed pattern matching redundancy analysis algorithm achieves a similar yield but 14.6% less RA time and 8.6 times higher reliability compared to the existing redundancy analysis algorithms.

Nanotechnology is an important technological alternative to overcome the limitations of complementary metal-oxide-semiconductor (CMOS) technology. Various circuit implementation methods based on nanotechnology have been proposed, and their most important characteristics are a high defect ratio and defect tolerance through circuit reconfiguration. CMOS-nanowire-MOLecular (CMOL) field-programmable gate array (FPGA) circuits are advanced logic circuit structures that combine the advantages of CMOS and nanotechnology. However, researches on defect diagnosis methods for the reconfiguration of CMOL FPGA circuits are barely conducted. In this paper, efficient circuit configuration methods for defect diagnosis of the CMOL FPGA circuits are proposed to address the problem. Also, diagnosis algorithms for both stuck-at open and stuck-at close defects are introduced. Experimental results show that with the proposed methods, diagnosis is possible for CMOL fabrics with up to 20% stuck-at open defects and 0.02% or more stuck-at close defects.

Cryptographic circuits generally are used for applications of wireless sensor networks to ensure security and must be tested in a manufacturing process to guarantee their quality. Therefore, a scan architecture is widely used for testing the circuits in the manufacturing test to improve testability. However, during scan testing, test-power consumption becomes more serious as the number of transistors and the complexity of chips increase. Hence, the scan chain reordering method is widely applied in a low-power architecture because of its ability to achieve high power reduction with a simple architecture. However, achieving a significant power reduction without excessive computational time remains challenging. In this paper, a novel scan correlation-aware scan cluster reordering is proposed to solve this problem. The proposed method uses a new scan correlation-aware clustering in order to place highly correlated scan cells adjacent to each other. The experimental results demonstrate that the proposed method achieves a significant power reduction with a relatively fast computational time compared with previous methods. Therefore, by improving the reliability of cryptography circuits in wireless sensor networks (WSNs) through significant test-power reduction, the proposed method can ensure the security and integrity of information in WSNs.

As the traditional IC design migrates to three-dimensional integrated circuits (3D-ICs) design, new challenges need to be considered carefully to solve its reliability and yield issues. 3D-ICs using through-silicon-vias (TSVs) can have latent defects such as resistive open and bridge defects, which are caused by the thermal stress during the fabrication process. These latent defects lead to the deterioration of the electrical performance of TSVs caused by an undesired increase in the resistance-capacitance (RC) delay. For this reason, various post-bond test methodologies have been studied to improve the reliability of 3D-ICs. Cost reduction in these TSV test architectures is also currently being studied by decreasing various factors such as hardware overhead, test time, and the peak current consumption. Usually, a single test-clock-period is required to determine whether the test result contains the defective TSV. When the test result of any TSVs fails, we use another single test-clock-period to classify its defect type. In this paper, we propose a new TSV test architecture to transfer the combined test output of the test result and the specific defect type to the pad during the single test-clock-period. Our proposed test architecture also provides a reliable block-based concurrent testing to optimize the test time by dividing the die into concurrent blocks. The experimental results showed that our proposed test architecture could reduce the test time and the hardware overhead substantially by ensuring that the reasonable peak power consumption for mass production was reasonable without the test quality being adversely affected.

This paper examined the historico-geographical background and current state of immigrants in the area designated as the “Mt. Chirisan Region,” their characteristics, and related integration issues. This article defines the Mt. Chirisan Region as the 7 cities/kuns of Namwŏn-si, Changsu-kun, Koksŏng-kun, Kurye-kun, Hadong-kun, Sanchŏng-kun, and Hamyang-kun. As the Mt. Chirisan Region mainly consists of mountainous and agricultural areas, the immigrant induction effect socio-economically was low relative to urban and industrial areas. It was also noted that, as the percentage of marriage immigration in Mt. Chirisan was high relative to urban or industrial areas, the female foreigner ratio was higher than that of male foreigners. In regard to the home countries of immigrants, women from South-East Asia and North-East Asia accounted for the majority. Also, this article examines the current situation of support programs of 7 local Multicultural Family Support Centers in the Mt. Chirisan Region, their problems, and probably solutions. Based on the historical development of the region and recent social changes, our society and government need to actively develop a higher level of social integration and employment education support programs, and carry out policies that will protect the diverse cultural identities of immigrants. In addition, differentiated multicultural family support programs appropriate for Mt. Chirisan, an inland mountain region, need to be developed.

Scan structures, which are widely used in cryptographic circuits for wireless sensor networks applications, are essential for testing very-large-scale integration (VLSI) circuits. Faults in cryptographic circuits can be effectively screened out by improving testability and test coverage using a scan structure. Additionally, scan testing contributes to yield improvement by identifying fault locations. However, faults in circuits cannot be tested when a fault occurs in the scan structure. Moreover, various defects occurring early in the manufacturing process are expressed as faults of scan chains. Therefore, scan-chain diagnosis is crucial. However, it is difficult to obtain a sufficiently high diagnosis resolution and accuracy through the conventional scan-chain diagnosis. Therefore, this article proposes a novel scan-chain diagnosis method using regression and fan-in and fan-out filters that require shorter training and diagnosis times than existing scan-chain diagnoses do. The fan-in and fan-out filters, generated using a circuit logic structure, can highlight important features and remove unnecessary features from raw failure vectors, thereby converting the raw failure vectors to fan-in and fan-out vectors without compromising the diagnosis accuracy. Experimental results confirm that the proposed scan-chain-diagnosis method can efficiently provide higher resolutions and accuracies with shorter training and diagnosis times.

While developing semiconductors, post-silicon validation is an important step to identify the errors that are not detected during the pre-silicon verification and manufacturing testing phases. When the design complexity increases, the required debug time also increases because additional debug data are required to identify the errors. In this study, we present a debug scheme that improves the error identification capability. The proposed debug approach concurrently generates three types of signatures using hierarchical multiple-input signature registers (MISRs). The error-suspect debug cycles are determined by analyzing the debug cycles that are commonly contained in the erroneous signatures of the three MISRs. To reduce the amount of debug data, we compare the high-level MISR signatures in real time with the golden signatures; further, we handle the remaining two MISRs based on the tag bits that are obtained from the results of the high-level MISR. The experimental results prove that the proposed debug structure can significantly improve the error identification capability using less debug data than that used in previous debug structure.

Energy efficiency enhancement has become an increasingly important issue for battery electric vehicles. Even if it can be improved in many ways, the driver’s driving pattern strongly influences the battery energy consumption of a vehicle. In this paper, eco assist techniques to simply implement an energy-efficient driving assistant system are introduced, including eco guide, eco control and eco monitoring methods. The eco guide is provided to control the vehicle speed and accelerator pedal stroke, and eco control is suggested to limit the output power of the battery. For eco monitoring, the eco indicator and eco report are suggested to teach eco-friendly driving habits. The vehicle test, which is done in four ways, consists of federal test procedure (FTP)-75, new european driving cycle (NEDC), city and highway cycles, and visual feedback with audible warnings is provided to attract the driver’s voluntary participation. The vehicle test result shows that the energy usage efficiency can be increased up to 19.41%.

This paper proposes a new DAC BIST (digital-to-analog converter built-in self-test) structure using a resistor loop known as a DDEM ADC (deterministic dynamic element matching analog-to-digital converter). Methods for both switch reduction and switch effect reduction are proposed for solving problems related to area overhead and accuracy of the conventional DAC BIST. The proposed BIST modifies the length of each resistor in the resistor loop via a merging operation and reduces the number of switches and resistors. In addition, the effect of switches is mitigated using the proposed switch effect reduction method. The accuracy of the proposed BIST is demonstrated by the reduction in the switch effect. The experimental results show that the proposed BIST reduces resource usages and the mismatch error caused by the switches.

Measurement and calibration of an analog-to-digital converter (ADC) using a histogram-based method requires a large volume of data and a long test duration, especially for a high resolution ADC. A fast and accurate calibration method for pipelined ADCs is proposed in this research. The proposed calibration method composes histograms through the outputs of each stage and calculates error sources. The digitized outputs of a stage are influenced directly by the operation of the prior stage, so the results of the histogram provide the information of errors in the prior stage. The composed histograms reduce the required samples and thus calibration time being implemented by simple modules. For 14-bit resolution pipelined ADC, the measured maximum integral non-linearity (INL) is improved from 6.78 to 0.52 LSB, and the spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are improved from 67.0 to 106.2dB and from 65.6 to 84.8dB, respectively.