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Background With the increase in life expectancy seen throughout the world, the prevalence of degenerative spinal pathology and surgery to treat it has increased. Spinal surgery under general anesthesia leads to various problems and complications, especially in patients with numerous medical comorbidities or elderly patients. For this reason, there is a need for safer anesthetic methods applicable to unhealthy, elderly patients undergoing spinal surgery. Purpose To report our experience with utilizing fluoroscopy-guided epidural anesthesia in conjunction with conscious sedation in spinal surgery. Patients and methods We performed a retrospective review of 111 patients at our institution that received fluoroscopy-guided epidural anesthesia for lumbar surgery from February to September 2018. Patients' records were evaluated to evaluate patient demographics, American Society of Anesthesiology Physical Classification System (ASA) class, and pain numerical rating scores (NRS) preoperatively and throughout their recovery postoperatively. Intraoperative data including volume of epidural anesthetic used, extent of epidural spread, and inadvertent subdural injection was collected. Postoperative recovery time was also collected. Results The mean age of our patients was 60 years old with a range between 31 and 83 years old. All patients experienced decreases in postoperative pain with no significant differences based on age or ASA class. There was no association between ASA class and time to recovery postoperatively. Older patients (age 70 years or greater) had a significantly longer recovery time when compared to younger patients. Recovery also was longer for patients who received higher volumes of epidural anesthesia. For every 1 mL increase of epidural anesthetic given, there was an increase in the extent of spread of 1.8 spinal levels. Conclusion We demonstrate the safety and feasibility of utilizing conscious sedation in conjunction with fluoroscopy-guided epidural anesthesia in the lumbar spinal surgery.

Background With the increase in life expectancy seen throughout the world, the prevalence of degenerative spinal pathology and surgery to treat it has increased. Spinal surgery under general anesthesia leads to various problems and complications, especially in patients with numerous medical comorbidities or elderly patients. For this reason, there is a need for safer anesthetic methods applicable to unhealthy, elderly patients undergoing spinal surgery. Purpose To report our experience with utilizing fluoroscopy-guided epidural anesthesia in conjunction with conscious sedation in spinal surgery. Patients and Methods We performed a retrospective review of 111 patients at our institution that received fluoroscopy-guided epidural anesthesia for lumbar surgery from February to September 2018. Patients’ records were evaluated to evaluate patient demographics, American Society of Anesthesiology Physical Classification System (ASA) class, and pain numerical rating scores (NRS) preoperatively and throughout their recovery postoperatively. Intraoperative data including volume of epidural anesthetic used, extent of epidural spread, and inadvertent subdural injection was collected. Postoperative recovery time was also collected. Results The mean age of our patients was 60 years old with a range between 31 and 83 years old. All patients experienced decreases in postoperative pain with no significant differences based on age or ASA class. There was no association between ASA class and time to recovery postoperatively. Older patients (age 70 years or greater) had a significantly longer recovery time when compared to younger patients. Recovery also was longer for patients who received higher volumes of epidural anesthesia. For every 1 mL increase of epidural anesthetic given, there was an increase in the extent of spread of 1.8 spinal levels. Conclusion We demonstrate the safety and feasibility of utilizing conscious sedation in conjunction with fluoroscopy-guided epidural anesthesia in the lumbar spinal surgery.

This paper presents a compact broadband branch-line hybrid coupler. It is composed of a miniaturized branch-line hybrid coupler and broadband impedance matching networks. A coupled-line structure is used for the broadband impedance matching network. The branch-line hybrid coupler is realized by using high-impedance transmission lines and distributed capacitors. In order to further reduce the circuit size, the distributed capacitors are placed in the center space of the hybrid coupler and the coupled lines are effectively meandered. For validation, a prototype of the compact hybrid coupler was designed and fabricated at the center frequency of 1 GHz. For given conditions, the proposed hybrid has 29.4% bandwidth which is from 870 to 1170 MHz. Compared to the conventional 3-dB branch-line hybrid coupler, it exhibited a size reduction of 50.8% and an extended operating bandwidth of 66.7%.

This article presents a highly integrated CMOS RF double-sideband (DSB) transmitter (TX) including an active input balun and a single-ended power amplifier (PA) for a ultrahigh frequency radiofrequency identification (RFID) system-on-chip reader. The conventional TX architecture, including an up-conversion mixer and a balanced PA, requires an output balun to create the needed single-ended load. Compared to the conventional TX architecture, the proposed system provides a more compact circuit and uses a smaller chip area because the active balun and the single-ended PA have a much smaller size than those using a passive balun and a differential PA. In addition, the gain of the active balun, which is generally larger than unity, can be a benefit in the system design budget. The designed TX IC is fabricated using a 0.13 μm CMOS process on a small area of 780 × 560 μm2 (including pads). The TX IC exhibited an overall conversion gain of 41.7 dB, an output P1dB of 18 dBm, an OIP3 of 28 dBm, a DSB noise figure of 14.8 dB, and a power consumption of 284.4 mW, including the 42.9 mW consumed by the local oscillator buffer stages. The implemented TX IC complied with the spectral mask for the DSB amplitude-shift keying signal of the RFID reader at an output power of 15.5 dBm. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:205–210, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27257

This article presents a simple complementary metal-oxide-semiconductor (CMOS) ring oscillator using a voltage-controlled delay and RS-latch, including a compensation circuit for the process and temperature variations.The compensation circuit, added to the original bias circuit, is a simple current sinker which is referenced through a current mirror circuit. The proposed oscillator was designed and implemented using a 0.13 μm CMOS process. The oscillator exhibited a significantly improved frequency variation of ±4.25% for a wide temperature range of from −40 to 80°C. Without the compensation circuit, the variation would have been ±13.39% from the center frequency of 2.33 MHz. The oscillator also showed a low sensitivity of 0.084% to process variation, according to a Monte-Carlo simulation with 1000 iterations. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:160–163, 2012, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26493

This letter presents the trade-off between size reduction and electrical performance of miniaturized branch line couplers using distributed capacitors placed in the inner open area of the hybrid. Based on single, double, and triple II-section approximations of the quarter wavelength transmission lines of a conventional design with high impedance lines and shunt metal-insulator-metal (MIM) capacitors, size reduction as well as electrical performance are compared both in simulation and experimentally. The miniaturized triple-section hybrid achieves similar bandwidth performance as the conventional 3 dB branch line hybrid coupler, but with a 61.2% smaller footprint. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1553–1556, 2010; Published online in Wiley InterScience (www.interscience. wiley.com). DOI 10.1002/mop.25273

In this paper, a design optimization approach for gallium-nitride (GaN)-based Doherty power amplifiers (PAs) is proposed to enhance linearizability and maximize the power-added efficiency (PAE) for multicarrier wideband code division multiple access (WCDMA) applications. This is based on the use of an input offset line at the peaking amplifier path to compensate, at a given backoff level, for the bias and power-dependant phase variation through the carrier and peaking paths. At a 6-dB output power backoff (OPBO), measurement results of the unsymmetrical unlinearized Doherty amplifier using a four-carrier WCDMA signal achieved results of close to 50% for the PAE and about -30 dBc for the adjacent channel leakage ratio. Linearization of the designed Doherty PA using a baseband digital predistortion technique led to quasi-perfect cancellation of spectrum regrowth. At an OPBO equal to the input signal's peak-to-average power ratio, -63- and -53-dBc adjacent channel power ratios were obtained when the Doherty amplifier was driven by single- and four-carrier WCDMA signals, respectively. To the best of the authors' knowledge, this represents the best reported results for PAE and linearity for GaN-based Doherty PAs linearized over 20 MHz of instantaneous bandwidth.

In this article, we analyzed and designed miniaturized third-order intermodulation distortion (IM3) generation circuits. An an- tiparallel Schottky diode pair was adopted for nonlinearity generation. A reflective configuration using a 90° hybrid coupler was employed to acquire a pure IM3 signal at the output. The fundamental signal at the output was automatically suppressed below the IM3 level using a reflec- tive load optimized for the fundamental impedance of the antiparallel diode pair. The IM3 generation characteristics were fully analyzed us- ing the Volterra series under a weak nonlinear assumption. A new opti- mum matching condition of the reflective load for the perfect fundamen- tal cancellation was derived. A miniaturized 12 14 mm 2 IM3 generator was designed and implemented for the 2.16 GHz band, based on the analysis results. The output performance measured for the imple- mented IM3 generator matched the calculated results. The IM3 genera- tor showed excellent fundamental cancellation characteristics and had a wide operational range for the input signal level. © 2009 Wiley Period- icals, Inc. Microwave Opt Technol Lett 51: 2137-2140, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24535

In this article, a high-power, high-efficiency inverted Doherty power amplifier (PA), having a more compact load network than that of the conventional Doherty amplifier, was designed and implemented for wide-band code-division multiple access (WCDMA) base-station applications. Its configuration and working principle are compared with the conventional Doherty amplifier. For experimental verification, we implemented an inverted Doherty amplifier, using a 190 W peak-envelope-power (PEP) laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistors (FETs). Using a four-carrier down-link WCDMA signal, we achieved a high power-added efficiency (PAE) of 32% and an average output power level as high as 46.3 dBm at a given adjacent channel leakage ratio (ACLR) level of -30 dBc. This is a 9.5% improvement in efficiency and 1 dB improvement in output power under the same ACLR conditions from those of the balanced class-AB operation using the same devices.

This paper proposes a methodology to design and optimize the footprint of miniaturized 3-dB branch-line hybrid couplers, which consists of high-impedance transmission lines and distributed capacitors. To minimize the physical size of the coupler, the distributed capacitors are placed within the empty space of the hybrid. The proposed design methodology calls for the joint optimization of the length of the reduced high-impedance transmission lines and the area of the distributed capacitors. A prototype at S-band was designed and built to validate the approach. It showed a size reduction by 62% compared with the conventional 3-dB branch-line hybrid coupler while providing similar performance and bandwidth.

In this article, we present an optimized Doherty power amplifier using an unequal quadrature input splitter and bias control for the peaking amplifier. The linearity and efficiency performances of the Doherty power amplifier were experimentally optimized by means of unequal quadrature input power splitters, which drive unbalanced input power between the carrier and peaking amplifiers. The bias points of the peaking amplifier were also adjusted for each input splitter. A high power-added efficiency of 33.68% and an output power of 33.95 dBm were achieved for a down-link wide-band code division multiple access signal excitation at a given adjacent channel leakage-power ratio of −30 dBc. This was a significant improvement by 2.75% and 8.22% points from the conventional Doherty and class-AB amplifiers, respectively. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1536–1539, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23420

In this paper, we propose a new compact load network for high-power Doherty amplifiers using an imperfect quarter-wave line. A compact pi-network quarter-wave transmission line, which consisted of two shunt capacitors and a series microstrip line, was used to replace a bulky microstrip transmission line. A simple L-C matching network was then deployed after the quarter-wave line. To take the inherent internal parasitic components in the packaged high-power transistors into account, the shunt capacitors of the pi-network quarter-wave transmission line were readjusted, which made an imperfect quarter-wave line. For verification, both the conventional and compact Doherty amplifiers were designed and implemented for the 859-MHz band using high-voltage laterally diffused metal-oxide-semiconductor field-effect transistors. The measured linearities and efficiencies of both amplifiers were compared to each other with respect to the reference performance of the class-AB amplifier for two-tone and down-link wideband code-division multiple-access signal excitations. The compact Doherty amplifier with a significantly reduced size for the load network by 75.7% performed even better than the conventional Doherty amplifier.

In this paper, we present a design method for a compact inverted Doherty power amplifier (IDPA), which has high-efficiency and high-power characteristics. An optimum load matching network and an additional offset line, after the matching network of the carrier amplifier, dynamically modulate the load impedance according to the input power drive, while the conventional Doherty power amplifier uses a quarter-wave line to do it. The operational principles and design guide are provided. For experimental verification, a 50-W Doherty amplifier was designed for the pi/4 differential quadrature phase-shift keying application at the 860-MHz band. The measured performance of the IDPA was compared with that of the balanced class-AB amplifier with the same output matching network. At an output power of 50 W, the IDPA performs with 3.16 dB better adjacent channel power ratio (-28 versus -24.84 dBc) and 6.15% higher power-added efficiency (59.02 versus 52.87%) than the class-AB amplifier does.

This experiment was conducted to investigate the effect of particles on the heat transfer characteristics of fluids flowing in a cold water tube. Plastic beads with 3 different sizes were used as flowing particles with cold water. An experimental test section was composed of concentric double tubes having diameters of 25mm for the inner tube and 50mm for the outer tube. The materials for the inner and outer tubes are copper and PVC respectively. It was found that the particles enhanced the heat transfer coefficient by random and vortex motion in the fluid. Hence the heat transfer coefficients for the fluid with 2㎜, 5㎜ and 2×6㎜ particles were 7%~37% higher than the fluid without the particles.

This paper presents a design method for a compact high-efficiency quasi-class-E amplifier, using a finite bias feed inductor. It is very difficult to achieve proper class-E operation from high-power transistors operating in the high-frequency region because of their internal parasitic components. To mitigate the effects of internal parasitic components on class-E operation, a finite DC feed inductance is introduced to resonate out the capacitive parasitic components. A quasi-class-E amplifier with a finite DC feed inductor was designed and implemented at 1.2 GHz using a high-power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET). We compared simulated time domain current and voltage waveforms with ideal ones. As the test results indicated, power-added efficiency as high as 70.4% was achieved, at high output power of 39.55 dBm, without losing the circuits' simplicity, one of the most important advantages of class-E operation. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1114–1118, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI.10.1002/mop.22368

We present a new linearization method for high-power amplifiers, using an envelope predistorter (EPD) including envelope delay taps and control circuits, for memory effect compensation. The lower and upper third-order intermodulation (IM3) components, generated by the EPD, can be separately controlled for their magnitudes and phases by the additional memory effect compensation circuits. By using experimental results for a high-power (30-W peak envelope power) class-AB amplifier, further linearity improvement was also demonstrated using the proposed EPD. For a two-tone signal with a tone spacing of 20 MHz, the proposed EPD, with only a single delay tap, cancelled the lower and upper IM3 components by 20.84 and 18.17 dB, while the conventional EPD, with no envelope delay tap, cancelled them by 11.67 and 8.50 dB, respectively

The wind turbine system has been studied widely in terms of the economic, efficiency and environmentally friendly. In the wind turbine system, the conventional generator is largely classified with the horizontal-axis generator and vertical-axis generator according to direction of rotation. The vertical axis wind generator has disadvantage such as low efficiency and narrow operation range than horizontal axis generator [1]. But it has been used because of the low production cost and driving irrespective of the wind direction. The AFPMSG with vertical axis structure has outstanding performances and characteristics such as high power, high torque density, and disuse of a commutator and slip-ring since rare-earth permanent magnet is applied in rotor [2-4].

Brushless DC Motor (BLDCM) is widely used in various fields such as the communication devices, the servo drives and home appliances on account of high efficiency, high power density, wide operating range and simple drive system. In addition, it is capable of designing in diverse structures compared with DC Motor because of arrangement of the armature winding and the permanent magnet. Furthermore, in the case of outer-rotor type motor, it is advantageous for the constant speed rotation due to inertia, and structurally stable since the magnets are attached to the inside of the yoke. This structure is used in many areas such as fan and blower motors [1], [2].

In this paper, we report the results of the experimental optimization of the 2nd-loop configuration for feedforward amplifiers in terms of their efficiency and linearity. We consider two parameters in the 2nd-loop of a feedforward amplifier: (i) the size ratio between the main and error amplifiers and (ii) the coupling factor of the error signal coupler. Experiments are performed using a multicarrier down-link WCDMA signal under various configurations. The measured data, which are normalized with respect to the overall power capacity of the main and error amplifiers, show that, among the different 2nd-loop configurations, the best compromised efficiency (13.4%) at a given adjacent channel leakage ratio (ACLR) level (−50 dBc) is observed for a size ratio of around 3.0 and a coupling factor of around 7.2 dB. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 617–621, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21425

We propose a load network, consisting of an optimized impedance transformer, for a Doherty amplifier. This load network allows the carrier and peaking amplifiers to have different load impedance. This results in better IM3 cancellation. Using a four-carrier down-link WCDMA signal, we achieved 0.95 dB higher output power level and 2.21% higher power-added efficiency compared to a conventional Doherty amplifier at an ACLR level of −30 dBc. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2502–2504, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24657

A high-power Cartesian feedback transmitter including a compact inverted Doherty amplifier is presented. The system efficiency was further improved using a bias line adjustment method for the compact inverted Doherty amplifier. After the bias line adjustment from a λ/4 line for the Doherty amplifier, a power-added efficiency (PAE) of 6.9% points was improved from 41.3 to 48.2% at an output power level of 45 dBm. The whole Cartesian feedback transmitter system exhibited an efficiency of 40% and an adjacent channel leakage ratio of-51 dBc at an output power of 45 dBm for 859 MHz band π/4-DQPSK applications. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 944–946, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23265

This paper presents a new design for a CMOS double-sideband (DSB) RF transmitter (TX) integrated circuit (IC) for UHF RF indentification (RFID) reader system-on-chip. Due to the strong demand for high linearity, low TX noise, and low cost, a CMOS passive up-conversion mixer with an adaptive bias circuit is proposed. High linearity of the passive mixer can be maintained over a wide range of dc levels from the dc-coupled IF signals using the proposed adaptive biasing circuit. A linear two-stage CMOS power amplifier (PA) follows the up-conversion mixer so that the overall third-order output intercept point (OIP3) of the two-stage PA is improved by the optimized design of the first stage in its biasing condition, the cell size, and due to inter-stage matching. The designed TX IC is fabricated using a 0.18-μm standard CMOS process and the implemented passive mixer exhibits a low double-sideband noise figure (DSB NF) of 4 dB and a high OIP3 of 13.3 dBm. The implemented PA exhibits a high-output 1-dB compression point (OP1dB) of 18 dBm, and a clear sweet spot in OIP3 of as high as 36.8 dBm at the two-tone average output power of 10 dBm. The implemented overall TX IC has a size of 960 × 670 × μm2 and the overall circuit performed with a gain of 17.8 dB, a high OP1dB of 17.6 dBm, an OIP3 of 28 dBm, and has a low DSB NF of 11.2 dB while consuming a biasing current of 58 mA from a 3.3-V supply. The proposed design also satisfies the spectral mask of the RFID standard for an output power of up to 18 dBm for the double-sideband amplitude shift-keying signals.

The paper proposes a new CMOS passive up-conversion mixer with an adaptive bias circuit providing a building block for the transmitter (TX) in UHF RFID reader devices implemented in system-on-chip (SoC) technologies. A high linearity of the passive mixer can be maintained over a wide range of DC levels at the DC-coupled IF signal, using the proposed adaptive bias circuit. The input DC voltage, sensed by the adaptive bias circuit, is shifted to an appropriate level, and supplied to the gates of the switching transistors so that the proper bias level of the switching transistor can be maintained. A CMOS passive mixer with the adaptive bias circuit has been designed and implemented using 0.18um CMOS technology and experimental results have shown that a conversion gain of −3.7dB, an input 1dB compression point (IP1dB) of 9dBm, a high input intercept point (IIP3) of 19dBm, and a double sideband noise figure (DSB NF) of 4dB can be achieved. The measured IIP3 can be maintained over a wide range of input DC voltages.

A miniaturized double-stage 3dB branch-line hybrid coupler using distributed capacitors in the inner area is proposed in this paper. It is composed of high impedance transmission lines with reduced length and distributed capacitors. Compared to a conventional double-stage branch-line hybrid coupler, which is typically used to obtain wider bandwidth than a single-stage approach can provide, the proposed topology allows for considerable size reduction, while maintaining similar electrical performance. For experimental validation, a conventional single-stage 3dB hybrid coupler, a conventional double-stage, and a miniaturized double-stage hybrid couplers are designed and fabricated. The size of the proposed miniaturized double-stage 3dB broadband branch-line hybrid coupler is reduced by 39.04% and 68.32% compared to a single-stage and a conventional double-stage branch-line hybrid coupler, respectively.

We present a 30 W Cartesian feedback transmitter with an efficiency of 40 % and an adjacent channel leakage power ratio (ACLR) of -51 dBc for 859 MHz band pi/4-DQPSK applications. The high efficiency of the system was achieved by a significant efficiency improvement for the final amplifier stage using a load modulation technique. The implemented Cartesian feedback transmitter, using a Doherty power amplifier, exhibited a 3rd order inter-modulation distortion (IMD3) improvement of 27 dB for a two-tone signal at an output power level of 45 dBm. It also had ACLR improvement of 16.2 dB for the pi/4-DQPSK signal at an output power level of 45 dBm. The system performed with an efficiency as high as 40 % which was an improved value by about 7 % points as a consequence of the high efficiency characteristics of the inverted Doherty amplifier.

We describe our proposal of an efficiency improvement method for a compact inverted Doherty amplifier using a bias line adjustment. In order to compensate for the capacitive parasitic components of the high-power transistors, we adjusted a lambda/4 bias line to have an inductive impedance value. The inductive bias line made parallel resonance with the capacitive internal component. The following matching network and offset line rotated the output reflection coefficient (GammaOUT) to almost -1, which was desirable for the compact inverted Doherty amplifier design. The optimum length of the bias line was found after some adjustments. Compared to the Doherty amplifier using a lambda/4 bias line, the proposed Doherty amplifier using an adjusted bias line provided improved power-added efficiencies (PAEs) of 6% and 4% points for a two-tone signal at an output power of 45 dBm and for the pi/4-DQPSK signal at an output power of 47 dBm, respectively.

We describe a RF predistorter (RFPD) which has multiple intermodulation (IM) paths for individual cancellation of IM3 and IM5 components. To compensate for the memory effect of the power amplifier and improve the linearization ability of the predistorter, we attached an additional IM3 path to the predistorter which had a delay mismatch against the original IM3 path. The optimized delay mismatch, phase, and magnitude of the additional IM3 components enabled the RFPD to moderately compensate for the memory effect of the IM3 components which were generated by the main amplifier. The proposed RFPD was experimentally verified at the 2.14 GHz band. Using a two-tone signal with a tone spacing of 20 MHz, the lower and upper IM3 components were cancelled by 26.21 and 22.84 dB, respectively. Without an additional IM3 path, the lower and upper IM3 components were only cancelled by 17.11 and 12.68 dB, respectively.

In this paper, the authors present an efficient design method for high efficiency class-F amplifiers considering active devices with internal parasitic components. Considering internal drain current/voltage waveforms observed at the internal drain current source of the transistor, harmonics control and fundamental matching circuits are optimized to have higher power-added efficiency (PAE). Two 1.2GHz amplifiers were designed using a large-signal model of an LDMOSFET: one had harmonics control circuits optimized for external current/voltage waveforms and another had them optimized for internal waveforms. Simulation of the class-F amplifiers with two different output networks was conducted. Class-F amplifiers having an output network optimized for internal waveforms had 19% higher PAE (79% versus 60%)

A dynamic bias switching technique is presented which discretely switches supply voltages according to the signal envelope level. For the detected envelope signals which are lower than an appropriate threshold, this technique dynamically switches the transistor's drain bias to a significantly lower voltage. For verification, a dynamic bias switching system, applied to a class-AB power amplifier for the 859 MHz band, was implemented. Using a down-link wideband code division multiple access (WCDMA) signal, improved output power of 0.5 dB from 30.5 to 31 dBm, and improved PAE of 8.1% points from 27.4 to 35.5% were achieved at a given ACLR level of −30 dBc compared to the conventional single-supplied class-AB amplifier.