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ABSTRACT Designing FFTs with higher radix butterfly units are increasingly in demand to combat the high throughput of 20 Gbps of the current 5G and 1 Tbps for beyond 5G technologies. Previous higher radix FFTs were implemented in FPGA, giving importance to area and power. This paper presents the design of radix‐power‐of‐2 butterfly circuit, using the proposed radix cosine coefficients' extractor equation that is applicable to all the inputs. This enables efficient pipelined shift‐add implementation of the required complex rotations. The proposed methodology encompasses the implementation of any power‐of‐two‐radix butterfly to realize large size FFT, essential for real‐time 5G and 6G applications. The proposed radix‐4, radix‐8, radix‐16, and radix‐32 architectures are implemented and verified on Xilinx Spartan‐7 FPGA using Vivado Design Suite (v2018). The results demonstrate that the proposed radix‐16 and radix‐32 architectures achieve a higher clock frequency, by a factor of 5.23 and 6.76, respectively, compared to the most recent literature. For performance analysis, the area‐delay and power‐delay products of the proposed radix‐16 and radix‐32 butterfly architecture are computed. The proposed radix‐16 butterfly architecture exhibits a 13.3% reduction in area‐delay product and a 34.25% decrease in power‐delay product compared to recent literatures. Similarly, the radix‐32 architecture shows a 27.31% lower area‐delay product and a 0.63% lower power‐delay product. [ABSTRACT FROM AUTHOR]

To improve the transconductance of operational transconductance amplifier (OTA), various architectures namely recycling folded cascode (RFC), Improved recycling folded cascode (IRFC), modified recycling folded cascode (MRFC) and high recycling folded cascode (HRFC) are existing in the literature. In this paper, further improvement in the transconductance of MRFC OTA can be achieved by shorting two nodes of its current mirror and is proposed as high modified recycling folded cascode (HMRFC) amplifier. The performance of the proposed HMRFC OTA is compared with the existing state of art OTAs. To validate the progressions in the specified parameters, recycling folded cascode (RFC), modified recycling folded cascode (MRFC) and high modified recycling folded cascode (HMRFC) OTAs are realized and implemented in UMC 180 nm process technology using Cadence Spectre for a bias current of 1.2 mA. Simulation results indicate that the proposed amplifier exhibits a DC gain of 79.47 dB, the slew rate of 194.2 V/µSec, UGB of 285.85 MHz and phase-margin of 77.12o for a load capacitance of 5 pF and also observed that the CMRR and FoMs of the proposed amplifier are better by a factor of 1.3 and 1.5 in comparison to RFC, and by a factor of 1.27 and 1.41 in comparison to MRFC OTAs respectively. [ABSTRACT FROM AUTHOR]

A modified recycling folded cascode (MRFC) operational transconductance amplifier (OTA) for achieving high DC gain, slew rate, and unity gain bandwidth (UGB) is proposed in this paper. Positive feedback is adopted to enhance DC gain and unity gain bandwidth. The proposed MRFC OTA is compared with conventional folded cascode (FC), recycling folded cascode (RFC), and other OTAs existing in the literature. Three OTAs, FC, RFC, and MRFC, are realized and implemented using the UMC 180 nm CMOS process for the same bias current of 300 μA. The designs are simulated in the Cadence Spectre Environment. From the simulation results, it may be noted that the proposed amplifier achieves a gain of 76.24 dB and unity gain bandwidth of 74.7 MHz with an input referred noise and slew rate of 139.2 μVrms and 64.05 V/μs respectively. The proposed amplifier occupies an area of 2760 μm2 . [ABSTRACT FROM AUTHOR]