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A new motion estimation method and its hardware implementation are presented in this paper. In this method, all the frames are firstly gray coded. After that, the two most significant bits from the...

This paper presents a one-dimensional-filtering-based constrained one-bit transformation (1D-C1BT)-based motion estimation to reduce the complexity of the High Efficiency Video Coding (HEVC) encoder. The proposed 1D-C1BT requires integer arithmetic additions, subtraction and shift operations to convert full resolution video frames to two bit depth 1D-C1BT frames. By embedding the 1D-C1BT in the HEVC encoder, the motion estimation (ME) complexity of the HEVC encoder is greatly reduced in terms of Motion Estimation Time (MET) and total Encoding Time (ET) in uni-prediction and bi-prediction respectively. From the experimental results, it is shown that the 1D-C1BT accompanying full search (FS) and test zonal search (TZS) algorithms greatly reduces MET and ET as compared to the FS and TZS algorithms of the HEVC encoder respectively. To further reduce the intricacy of the HEVC encoder in the fast search mode, star-diamond (SD) search accompanying 1D-C1BT is proposed. The 1D-C1BT accompanying SD further reduces MET and ET with small increment in Bjontegaard Delta Rate and small decrement in Bjontegaard Delta Peak Signal to Noise Ratio, compared to the TZS algorithm of the HEVC encoder. In the FS mode of the HEVC encoder, the proposed 1D-C1BT, accompanying FS, reduces MET by 86.00% and ET by 83.94%, with BD-Rate of 0.1452% and BD-PSNR of 0.2635% in low delay-P main profile. The proposed ME algorithms, 1D-C1BT accompanying full search (FS + 1D-C1BT), 1D-C1BT accompanying test zonal search (TZS + 1D-C1BT) and 1D-C1BT accompanying star diamond search (SD + 1D-C1BT) greatly reduce ME complexity in all the three configurations (low delay-P, low delay-B and random access main profile) of the HEVC encoder.

In this work, a copper-doped (5%) zinc oxide (Cu:ZnO) ferroelectric materials-based memristor model was realized and it was employed to develop principal component analysis (PCA), a data dimension reduction technique. The developed PCA was utilized to efficaciously classify breast cancer datasets, which are considered as complex and big volumes of data. It was found that the controllable memristance variations were analogous to the weight modulations in the implemented neural network-based learning systems. Sanger’s rule was utilized to achieve unsupervised online learning in order to generate the principal components. On one side, the developed memristor-based PCA network was found to be effective to isolate distinct breast cancer classes with a high classification accuracy of 97.77% and the error in the classification of malignant cases as benign of 0.529%, a significantly low value. On the other side, the power dissipation was found to be 0.27 µW, which suggests the proposed memristive network is suitable for low-power applications. Further, a comparison was established with other existing non-memristor and non-PCA-based data classification systems. Furthermore, the devised less complex equations to implement PCA on this memristive crossbar array could be employed to implement any neural network algorithm.

The Discrete Cosine Transform (DCT) plays a major role in many video coding standards such as High Efficiency Video Coding (HEVC). In this paper, a new algorithm that generates low complexity DCT approximation matrices with minimum number of low-frequency coefficients for all transform sizes 8, 16 and 32, is proposed. This algorithm accelerates the HEVC encoder in terms of total encoding time (ΔET) by 39.93% with a small (0.6104%) increase in bitrate and a small (0.5489 dB) decrease in Peak Signal to Noise Ratio.

In this paper, a low complexity motion estimation algorithm based on a two-step search on gray coded video frames has been proposed. In this method, motion estimation is done in two steps. Firstly, a crude motion vector is obtained by performing motion estimation on the two most significant bits from the gray coded bit planes. The refinement of the motion vectors which were obtained from the first stage is then done on the gray coded image frames with 8 bits/pixel representation. In addition, a search pattern with an adaptive nature is used in the second stage of motion estimation instead of the full search. The proposed algorithm has been tested on several benchmark video sequences, and it is found that its performance is superior to a recently reported motion estimation algorithm.

The major concern of the present world is the increase in criminal activities that are taking place throughout the world. The criminal activities in today’s world include murder, theft, rape, women exploitation, human trafficking, possession of illegal properties, kidnapping. This paper summarizes the criminal activities related to female kidnapping in India. This paper highlights the statistical analysis of female kidnapping in India and thereby develops a predictive model to envisage the purpose of kidnapping of an individual female based on certain parameters. The model is developed using the decision tree technique by applying Iterative Dichotomizer (ID3) algorithm. The ID3 algorithm uses the entropy measure as a criterion for selecting classifiers for branching. The raw data set is converted to an appropriate one by converting the categorical values to numerical values using label and one hot encoding. This model is then trained with the appropriate training data set, and then, its performance is evaluated with a testing data set. The efficiency of the model is detected with the measures of accuracy, precision, recall, F1, AUC scores.

An efficient architecture that implements motion estimation based on a combination of diamond search algorithm and weighted constrained one-bit transformation is presented. The component of any motion estimation hardware that deals with the memory access consumes considerable power. This paper reports efforts at exploiting the overlap of search data among various search locations to reduce the number of memory accesses. The proposed architecture can reduce total power consumption by up to 23% compared to a recently reported architecture. Moreover, only 9 processing elements are used in this architecture, as against 16 processing elements used in conventional one bit transformation based motion estimation hardware. This in turn substantially reduces the total area of the architecture. As the proposed architecture is area efficient in addition to consuming relatively less power, its potential application lies in portable consumer video playback systems typically operated by batteries.

A new block matching algorithm and its VLSI architecture for performing Motion Estimation (ME) are presented in this paper. In the reported fast two stage search algorithm, ME is performed in two stages. In the first stage, pixel truncation is used. In the second stage, ME is performed with full pixel resolution with an adaptive search pattern. The main advantage of the proposed algorithm is the inclusion of an early termination mechanism to reduce overall power consumption for the resulting architecture. The paper also introduces a suitable architecture to implement the proposed ME algorithm. In this architecture, a new memory management scheme has been proposed so that different bit planes can be accessed at different stages of ME from the same memory module. It has been shown that the proposed architecture can save approximately 27% power compared to another recently reported architecture. The proposed architecture can therefore be considered suitable for portable, battery-powered video consumer devices1.

In the present paper, architectures implementing fixed block size and variable block size (VBS) motion estimation (ME) algorithms on one bit transformed (1-BT) image frames have been presented. The proposed architectures perform ME by applying diamond search (DS) algorithm on 1-BT image frames. The 1-BT based ME is usually performed by applying full search (FS) algorithm. Our simulation results reveal that the application of DS on 1-BT based ME can significantly reduce the computational complexity which is observed in FS based 1-BT ME at a tolerable degradation in the quality. In terms of latency, the architectures have been shown to be superior to several other 1-BT ME architectures. The presented DS based 1-BT ME architectures have succeeded in reducing the minimum clock frequency required to process a video sequence with a given frame size and frame rate, which in turn reduces the overall power consumption compared with other ME architectures. In particular, for processing SDTV sequences (1280×720 @ 30 fps), the power consumption by the proposed VBS ME architecture is reduced by at least 41% compared to the other 1-BT based ME architectures available in literature. The proposed architectures are therefore, considered suitable for low-power portable video applications typically operated by battery power.

This chapter begins with an overview of block matching algorithm (BMA) approach to motion estimation which is preferred for its simplicity and straightforward circuit implementation.

The main aim of this chapter is to provide the fundamentals of wavelet based Scalable Video Coding (SVC), and to briefly discuss about its two widely followed variants, viz.

The goal of this chapter is to introduce a new block matching algorithm, namely the Fast Two Stage Search (F2SS) algorithm and its VLSI architecture for performing low power variable block size Motion Estimation (ME) based on pixel truncation. The chapter starts with a brief discussion on ME methods which adopt the pixel truncation approach.

The goal of this chapter is to introduce a Fast Three Step Search (FTSS) algorithm, and its VLSI architecture.

The present paper proposes a fast algorithm and its VLSI architecture for fast quarter pixel (QP) accurate motion estimation (ME). The proposed algorithm is based on the distribution of the QP motion vectors (MVs) around the half pixel MV. The proposed algorithm efficiently explores the most likely QP locations and therefore skips the unlikely ones. The number of QP search locations for the proposed algorithm is reduced by 50% compared to the original full search method but results in only about 0.12 dB peak signal to noise ratio degradation. The VLSI architecture of the proposed algorithm theoretically can process thirty three 1280×720 HDTV frames per second. The power consumption of the proposed architecture is also reduced by 15? compared to a recently reported architecture.

This paper proposes a parallel architecture for Fast Two-Step Search algorithm, which is used in sub-pixel motion estimation with reduced complexity. As frequent data access is necessary to execute the algorithm which involves interpolation, an architecture efficient in terms of the memory bandwidth is suitable for implementing the algorithm. In the present paper, an architecture based on an intelligent memory configuration has been proposed for the implementation of Fast Two-Step Search algorithm for half-pixel motion estimation. The proposed architecture is based upon nine processing elements (PEs) accompanied with the use of intelligent data arrangement and memory configuration. The proposed architecture is designed to be used as part of H.264 video coding. The architecture, which has been synthesized under Synopsys Design Vision environment, can work at a frequency up to 90 MHz while consuming a power of approximately 459 mW. The proposed architecture provides the solution for realtime low bit rate video applications.

The present article proposes a high-performance architecture for the Two-Step Search algorithm, which is used in half-pixel motion estimation. As motion estimation calls for intense computation on a large number of pixels stored in memory, frequent memory access is involved in this operation. In the present article, an architecture, which is based on an intelligent memory configuration to contain the required large memory bandwidth, has been proposed for implementing the Two-Step Search algorithm for variable block sizes as recommended by H.264 standard. The present architecture has been compared with a reported architecture. It has been found that the proposed architecture can process up to 33% more number of High Definition Tele-Vision frames (of size 1280×720) and also consumes 5% less power by sacrificing only about 1.6% of the total chip area.