Search

Low temperature complementary metal oxide semiconductor (CMOS) or cryogenic CMOS is a promising avenue for the continuation of Moore's law while serving the needs of high performance computing. With temperature as a control “knob” to steepen the subthreshold slope behavior of CMOS devices, the supply voltage of operation can be reduced with no impact on operating speed. With the optimal threshold voltage engineering, the device ON current can be further enhanced, translating to higher performance. In this article, the experimentally calibrated data was adopted to tune the threshold voltage and investigated the power performance area of cryogenic CMOS at device, circuit and system level. We also presented results from measurement and analysis of functional memory chips fabricated in 28 nm bulk CMOS and 22 nm fully depleted silicon on insulator (FDSOI) operating at cryogenic temperature. Finally, the challenges and opportunities in the further development and deployment of such systems were discussed.

Cryogenic operation of CMOS transistors (i.e., cryo-CMOS) effectively brings an ultrasteep subthreshold slope (SS) and ultralow leakage, enabling high energy efficiency with appropriate tuning of threshold voltage and supply voltage. On the other hand, cryo-CMOS suffers from elevated sensitivity to process and voltage variations. To facilitate early-stage design exploration, we develop predictive BSIM-CMG model cards, which are calibrated with 14 nm TCAD simulation and our experimental FinFET data from 300 to 77 K. These models are scalable with temperatures from 300 K down to 77 K, device engineering and variations. Based on them, we benchmark various circuit examples to illustrate the tremendous potential of cryo-CMOS for energy-efficient computing, in the presence of process variations. For logic circuits, such as a canonical critical path, more than $15\times $ reduction in total energy consumption is demonstrated at 77 K for the iso–Delay condition, compared to the operation at the room temperature (RT). The presence of variations only has a marginal impact on energy efficiency, after threshold voltage and supply voltage are adaptively increased. For static noise margin (SNM), it is consistently improved at 77 K. However, the impact of variations on SNM is much more pronounced than that on logic circuits.

Modern computers require an exponential increase in resources when solving computationally hard problems, motivating the need for an alternative computing platform to solve such problems in an energy‐efficient manner. Vertex coloring, a nondeterministic polynomial time (NP‐hard) combinatorial optimization problem, is one such problem. Herein, an experimental demonstration of using cardiac cell‐based bio‐oscillator network coupling dynamics to solve a vertex coloring problem in various scales of graphs using a simple cell patterning method to construct scalable and controlled cardiac cell networks is presented. Although there are limitations to using these cardiac cells as oscillators, such as their low frequency compared to complementary metal–oxide–semiconductor (CMOS) oscillators, that result in longer processing times, the accuracy in large graph instances, the significantly less amount of energy consumption, and the ease of fabrication and potential to extend this system to massively parallel 3D structures make the bio‐oscillators a promising new platform for collective computing applications.

Neural sampling machines make use of noise to perform learning. Here, Dutta et al. present a hybrid stochastic synapse composed out of a ferroelectric transistor combined with a stochastic selector exhibiting multiplicative synaptic noise required for implementing a neural sample machine.

Analog and RF mixed-signal cryogenic-CMOS circuits with ultrahigh gain-bandwidth product can address a range of applications such as interface circuits between superconducting (SC) single-flux quantum (SFQ) logic and cryo-dynamic random-access memory (DRAM), circuits for sensing and controlling qubits faster than their decoherence time for at-scale quantum processor. In this work, we evaluate RF performance of 18 nm gate length ( $L_{G}$ ) fully depleted silicon-on-insulator (FDSOI) NMOS and PMOS from 300 to 5.5 K operating temperature. We experimentally demonstrate extrapolated peak unity current-gain cutoff frequency ( $f_{T}$ ) of 495/337 GHz ( $1.35\times /1.25\times $ gain over 300 K) and peak maximum oscillation frequency ( $f_{\mathrm {MAX}}$ ) of 497/372 GHz ( $1.3\times $ gain) for NMOS/PMOS, respectively, at 5.5 K. A small-signal equivalent model is developed to enable design-space exploration of RF circuits at cryogenic temperature and identify the temperature-dependent and temperature-invariant components of the extrinsic and the intrinsic FET. Finally, performance benchmarking reveals that 22 nm FDSOI cryogenic RF CMOS provides a viable option for achieving superior analog performance with giga-scale transistor integration density.

Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high-performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in the cryogenic operation of digital logic. In this article, we analyze digital standard cells in a 28 nm high- $k$ metal gate (HKMG) CMOS foundry process design kit (PDK). We have developed Berkeley Short-channel IGFET Model (BSIM)4 of cryogenic CMOS and calibrated them with experimental measurements. Since low-temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this article, we present inverter static and dynamic characteristics and multiple ring oscillator (RO) structures. The simulation study shows that we can achieve 28% (FO4-RO) – 59% (NAND3-RO) higher performance under iso- $V_{\mathrm {DD}}$ scenario and up to 90% improvement in the energy-delay product (EDP) under iso-overdrive scenario at 6 K compared to room temperature.

Many combinatorial optimization problems can be mapped onto the ground-state search problem of an Ising model. Exploiting the continuous-time dynamics of a network of coupled phase-transition nano-oscillators (PTNOs) allows building an Ising Hamiltonian solver for obtaining optimum or near-optimum solution with a large speed-up over discrete-time iterative digital hardware. Here, we provide insights into the continuous-time dynamics of such a PTNO-based Ising Hamiltonian solver. We highlight the formation of stable attractor states in the phase space of the coupled PTNO network using second-harmonic injection locking (SHIL) that corresponds to the minima of the Ising Hamiltonian. We show that the emergent synchronized dynamics of the PTNO network is maximized near the critical point of oscillator phase bistability beyond which the dynamics is limited by freeze-out effects. Such dynamical freeze-out severely limits the performance of the PTNO-based Ising solver from obtaining the global optimum. We highlight an improvement in the success probability of reaching the ground state by introducing an annealing scheme with linearly increasing SHIL amplitude compared with a constant SHIL. Finally, we estimate the “effective temperature” of the PTNO-based Ising solver by comparing it with the Markov chain Monte Carlo simulations. The PTNO-based Ising solver behaves like a low-temperature Ising spin system, indicating its effectiveness for optimization tasks.

Designing alternative paradigms for bio-inspired analog computing that harnesses collective dynamics remains a challenge. Here, the authors exploit the synchronization dynamics of coupled vanadium dioxide-based insulator-to-metal phase-transition nano-oscillators for adaptive locomotion control.

High static power associated with static random access memory (SRAM) represents a bottleneck in increasing the amount of on-chip memory. Novel, emerging nonvolatile memories such as spintransfer torque magnetic random access memory (STT-RAM), resistive random access memory (RRAM), and ferroelectric field effect transistor-based random access memory (FeFET-RAM) are alternatives for replacing hardware kernels such as SRAM-based last level caches (LLC) due to their fast access times and lower leakage. In this paper, we study an ultra-dense FeFET-RAM based on 1-FeFET memory cells, and address potential disturbance issues at the array level. Disturbances are studied experimentally and via simulation. Experimental measurements are well correlated with modeling results suggesting that we have a good understanding of how disturbance issues will manifest themselves. That said, previous WRITE schemes for 1-FeFET arrays may: 1) exacerbate disturbances and 2) significantly degrade figures of merit (FoM) such as WRITE power. To address these issues, we propose the use of columnwise body connections to simultaneously overcome disturbances and reduce leakage currents during WRITES. We present detailed studies on how 1-FeFET memory cells and arrays (with columnwise body bias) fare when compared to traditional SRAM approaches and other emerging technologies. Notably, we benchmark the 1-FeFET memory against 1T + 1FeFET and 2T + 1FeFET designs proposed in early works, as well as SRAM, STTRAM, and RRAM. Our evaluation of a 64×64 FeFET-RAM array shows that the area, READ delay, and static power are reduced by ~5.3×, ~1.5×, and ~74×, respectively, when compared to an SRAM equivalent. Also, the 1-FeFET memory cell design shows ~50× improvements in terms of WRITE energy with respect to STTRAM and RRAM counterparts.

In recent years, several designs that use in-memory processing to accelerate machine-learning inference problems have been proposed. Such designs are also a perfect fit for discrete, dynamic, and distributed systems that can solve large-dimensional optimization problems using iterative algorithms. For in-memory computations, ferroelectric field-effect transistors (FerroFETs) owing to their compact area and distinguishable multiple states offer promising possibilities. We present a distributed architecture that uses FerroFET memory and implements in-memory processing to solve a template problem of least squares minimization. Through this architecture, we demonstrate an improvement of 21× in energy efficiency and 3× in compute time compared to a static random access memory (SRAM)-based processing-inmemory (PIM) architecture.

Current rate of data generation and the need for real‐time data analytics can benefit from new computational approaches where computation proceeds in a massively parallel way while being scalable and energy efficient. Biological systems arising from interaction of living cells can provide such pathways for sustainable computing. Current designs for biocomputing leveraging the information processing units of the cells, such as DNA, gene, or protein circuitries, are inherently slow (hours to days speed) and, therefore, are primarily being considered for archival storage of information. On the contrary, electrically active cells that can synchronize in milliseconds and can be connected as networks to perform massively parallel tasks can transform biocomputing and lead to novel ways of high throughput information processing. Herein, coupled oscillator networks made of living cardiac muscle cells, or bio‐oscillators, is explored as collective computing components for solving computationally hard problems. An empirically validated circuit compatible macromodel is developed for the bio‐oscillators and the fibroblast cells acting as coupling elements, to faithfully reproduce the synchronization dynamics of the network and it is shown that such bio‐oscillator network can be scaled up to hundreds of nodes and be used to solve computationally hard problems faster than traditional heuristics‐based Boolean algorithms.

The two possible pathways toward artificial intelligence (AI)—(i) neuroscience-oriented neuromorphic computing [like spiking neural network (SNN)] and (ii) computer science driven machine learning (like deep learning) differ widely in their fundamental formalism and coding schemes (Pei et al., 2019). Deviating from traditional deep learning approach of relying on neuronal models with static nonlinearities, SNNs attempt to capture brain-like features like computation using spikes. This holds the promise of improving the energy efficiency of the computing platforms. In order to achieve a much higher areal and energy efficiency compared to today’s hardware implementation of SNN, we need to go beyond the traditional route of relying on CMOS-based digital or mixed-signal neuronal circuits and segregation of computation and memory under the von Neumann architecture. Recently, ferroelectric field-effect transistors (FeFETs) are being explored as a promising alternative for building neuromorphic hardware by utilizing their non-volatile nature and rich polarization switching dynamics. In this work, we propose an all FeFET-based SNN hardware that allows low-power spike-based information processing and co-localized memory and computing (a.k.a. in-memory computing). We experimentally demonstrate the essential neuronal and synaptic dynamics in a 28 nm high-K metal gate FeFET technology. Furthermore, drawing inspiration from the traditional machine learning approach of optimizing a cost function to adjust the synaptic weights, we implement a surrogate gradient (SG) learning algorithm on our SNN platform that allows us to perform supervised learning on MNIST dataset. As such, we provide a pathway toward building energy-efficient neuromorphic hardware that can support traditional machine learning algorithms. Finally, we undertake synergistic device-algorithm co-design by accounting for the impacts of device-level variation (stochasticity) and limited bit precision of on-chip synaptic weights (available analog states) on the classification accuracy.

We report a fully transparent thin-film transistor utilizing a La-doped BaSnO3 channel layer that provides a drain current of 0.468 mA/μm and an on-off ratio of 1.5 × 108. The La-doped BaSnO3 channel is grown on a 100–150 nm thick unintentionally doped BaSnO3 buffer layer on a (001) MgO substrate by molecular-beam epitaxy. Unpatterned channel layers show mobilities of 127–184 cm2 V−1 s−1 at carrier concentrations in the low to mid 1019 cm−3 range. The BaSnO3 is patterned by reactive ion etching under conditions preserving the high mobility and conductivity. Using this patterning method, a sub-micron-scale thin film transistor exhibiting complete depletion at room temperature is achieved.

Interstitial trapping by oxygen-inserted silicon channel results in blocking of boron and phosphorus transient enhanced diffusion as well as retention of channel boron profiles during the gate oxidation process. The enhanced doping profile control capability is applicable to punch-through stop of advanced CMOS devices and its benefits to 28 nm planar CMOS and 20 nm bulk FinFET devices projected by TCAD are discussed.

Abstract While Boolean logic has been the backbone of digital information processing, there exist classes of computationally hard problems wherein this paradigm is fundamentally inefficient. Vertex coloring of graphs, belonging to the class of combinatorial optimization, represents one such problem. It is well studied for its applications in data sciences, life sciences, social sciences and technology, and hence, motivates alternate, more efficient non-Boolean pathways towards its solution. Here we demonstrate a coupled relaxation oscillator based dynamical system that exploits insulator-metal transition in Vanadium Dioxide (VO2) to efficiently solve vertex coloring of graphs. Pairwise coupled VO2 oscillator circuits have been analyzed before for basic computing operations, but using complex networks of VO2 oscillators, or any other oscillators, for more complex tasks have been challenging in theory as well as in experiments. The proposed VO2 oscillator network harnesses the natural analogue between optimization problems and energy minimization processes in highly parallel, interconnected dynamical systems to approximate optimal coloring of graphs. We further indicate a fundamental connection between spectral properties of linear dynamical systems and spectral algorithms for graph coloring. Our work not only elucidates a physics-based computing approach but also presents tantalizing opportunities for building customized analog co-processors for solving hard problems efficiently.

As computational models inspired by the biological neural system, spiking neural networks (SNN) continue to demonstrate great potential in the landscape of artificial intelligence, particularly in tasks such as recognition, inference, and learning. While SNN focuses on achieving high-level intelligence of individual creatures, Swarm Intelligence (SI) is another type of bio-inspired models that mimic the collective intelligence of biological swarms, i.e., bird flocks, fish school and ant colonies. SI algorithms provide efficient and practical solutions to many difficult optimization problems through multi-agent metaheuristic search. Bridging these two distinct subfields of artificial intelligence has the potential to harness collective behavior and learning ability of biological systems. In this work, we explore the feasibility of connecting these two models by implementing a generalized SI model on SNN. In the proposed computing paradigm, we use SNNs to represent agents in the swarm and encode problem solutions with the spike firing rate and with spike timing. The coupled neurons communicate and modulate each other's action potentials through event-driven spikes and synchronize their dynamics around the states of optimal solutions. We demonstrate that such an SI-SNN model is capable of efficiently solving optimization problems, such as parameter optimization of continuous functions and a ubiquitous combinatorial optimization problem, namely, the traveling salesman problem with near-optimal solutions. Furthermore, we demonstrate an efficient implementation of such neural dynamics on an emerging hardware platform, namely ferroelectric field-effect transistor (FeFET) based spiking neurons. Such an emerging in-silico neuron is composed of a compact 1T-1FeFET structure with both excitatory and inhibitory inputs. We show that the designed neuromorphic system can serve as an optimization solver with high-performance and high energy-efficiency.

Os princípios requeridos para uma Classificação geral e métodos a serem aplicados em indexação pré-coordenada foram examinados e baseados na evidência psicológica da natureza do conhecimento.Um esquema compatível a ambos foi delineado. Para tanto sentiu-se a necessidade de uma divisão primária em tipos de conceitos básicos, a subdivisão destes em várias colunas paralelas, o arranjo de termos ou conceitos em cada coluna, em diferentes níveis de complexidade, a representação de classes genéricas em qualquer nível, e uma apresentação em separado de tipos mais complexos de conceitos ou termos que são heterogêneos em relação aos tipos de conceitos básicos. Estas diferentes linhas de desenvolvimento de conceitos podem ser representadas por diferentes direções em um diagrama multidimensional. As diferentes dimensões apresentam as relações fundamentais entre conceitos. Outras relações menos fundamentais, portanto não incorporadas, podem ser introduzidas em forma de símbolos entre conceitos expressando relações explícitas. Esse esquema que pode ser melhor denominado "organização de conceitos", ao invés de classificação, é particularmente valioso em recuperação da informação. http://revista.ibict.br/ciinf/article/view/88

Artificial neural networks can harness stochasticity in multiple ways to enable a vast class of computationally powerful models. Boltzmann machines and other stochastic neural networks have been shown to outperform their deterministic counterparts by allowing dynamical systems to escape local energy minima. Electronic implementation of such stochastic networks is currently limited to addition of algorithmic noise to digital machines which is inherently inefficient; albeit recent efforts to harness physical noise in devices for stochasticity have shown promise. To succeed in fabricating electronic neuromorphic networks we need experimental evidence of devices with measurable and controllable stochasticity which is complemented with the development of reliable statistical models of such observed stochasticity. Current research literature has sparse evidence of the former and a complete lack of the latter. This motivates the current article where we demonstrate a stochastic neuron using an insulator-metal-transition (IMT) device, based on electrically induced phase-transition, in series with a tunable resistance. We show that an IMT neuron has dynamics similar to a piecewise linear FitzHugh-Nagumo (FHN) neuron and incorporates all characteristics of a spiking neuron in the device phenomena. We experimentally demonstrate spontaneous stochastic spiking along with electrically controllable firing probabilities using Vanadium Dioxide (VO2) based IMT neurons which show a sigmoid-like transfer function. The stochastic spiking is explained by two noise sources - thermal noise and threshold fluctuations, which act as precursors of bifurcation. As such, the IMT neuron is modeled as an Ornstein-Uhlenbeck (OU) process with a fluctuating boundary resulting in transfer curves that closely match experiments. The moments of interspike intervals are calculated analytically by extending the first-passage-time (FPT) models for Ornstein-Uhlenbeck (OU) process to include a fluctuating boundary. We find that the coefficient of variation of interspike intervals depend on the relative proportion of thermal and threshold noise, where threshold noise is the dominant source in the current experimental demonstrations. As one of the first comprehensive studies of a stochastic neuron hardware and its statistical properties, this article would enable efficient implementation of a large class of neuro-mimetic networks and algorithms.

Os princípios requeridos para uma classificação geral e métodos a serem aplicados em indexação pré-coordenada foram examinados e baseados na evidência psicológica da natureza do conhecimento.Um esquema compatível a ambos foi delineado. Para tanto sentiu-se a necessidade de uma divisão primária em tipos de conceitos básicos, a subdivisão destes em várias colunas paralelas, o arranjo de termos ou conceitos em cada coluna, em diferentes níveis de complexidade, a representação de classes genéricas em qualquer nível, e uma apresentação em separado de tipos mais complexos de conceitos ou termos que são heterogêneos em relação aos tipos de conceitos básicos. Estas diferentes linhas de desenvolvimentode conceitos podem ser representadas por diferentes direções em um diagrama multidimensional. As diferentes dimensões apresentam as relações fundamentais entre conceitos. Outras relações menos fundamentais, portanto não incorporadas, podem ser introduzidas em forma de símbolos entre conceitos expressando relações explícitas. Esse esquema que pode ser melhor denominado"organização de conceitos", ao invés de classificação, é particularmente valioso em recuperação da informação. Abstract The desirable principles required for a general classification and methods to be applied inpre-coordinate indexing have been examined and are based on some psychological evidence of the nature of knowledge. A scheme compatible withboth has been devised. This has been found to require a primary division into basic concept types, the subdivision of these types into several parallel columns, the arrangement of terms orconcepts, within each column, at different levels of complexity, the representation of generic classesat any level, and a separate display of morecomplex types of concept or terms which areheterogenous with respect to the basic concept types. These different lines of development of concepts can be represented by different directions in a multidimensional diagram. The different dimensions display the fundamental relations between concepts. Other less fundamental relations not thus incorporated can be introduced in the form of symbols between concepts expressing explicit relations. Such a scheme which is now better called 'concept organization' than classification is particularly valuable for information retrieval.