III-V materials are considered as alternative channel materials to silicon beyond the 22 nm CMOS technology node due to their high electron mobility. However, the fabrication of high-performance III-V MOSFETs has long been elusive, primarily due to the lack of a high-quality native oxide for IIIVs analogous to that of silicon. Therefore, there has been an enormous effort to identify thermodynamically stable dielectrics which can also unpin the Fermi level. This includes the use of aSi and a-Ge interfacial layers, molecular beam epitaxy (MBE) grown Ga2O3(Gd2O3) and atomic layer deposition (ALD) of Al2O3 and HfO2. It is known that arsenic oxides are the potential cause of the Fermi level pinning in III-V MOS structures. Therefore, eliminating III-V native oxides at the interface of high-k/III-V layer is extremely crucial. On the other hand, integrating ALD high-k on III-V necessitates an effective surface chemical treatment, in order to mitigate the strong Fermi level pinning at the high-k/III-V interface. This surface treatment should also facilitate achieving full surface coverage from the beginning of the ALD run, while ruling out the re-growth of native oxides during the ex situ sample transfer to the ALD reactor. We have recently demonstrated that employing a simple wet clean in dilute HF followed by sulfur passivation in (NH4)2S can effectively improve the electrical characteristics of GaAs MOS capacitors. Moreover, the selective reduction and subsequent removal of GaAs native oxides upon ALD of high-k using an appropriate choice of precursor chemistry can eliminate the need for an elaborate in situ clean prior to the deposition of the high-k layer. In this work, we have examined the interfacial selfcleaning attribute of ALD-Al2O3 and HfO2 on GaAs substrates using trimethyl aluminum (TMA) and tetrakis (ethylmethyamido) hafnium (TEMAH) precursors by x-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM). Capacitance-voltage (C-V) characteristics of GaAs MOS capacitors with HfAlO gate dielectrics were monitored. Furthermore, we report the fabrication of n-channel self-aligned inversion-type enhancement-mode (E-mode) GaAs MOSFETs with ALD-Al2O3 gate dielectric directly on GaAs. In order to examine the interfacial self-cleaning attribute of ALD-Al2O3 and HfO2 using TMA and TEMAH precursors respectively, 2-nm thick high-k layers were grown on p-type GaAs substrates with no chemical treatment. Figure 1(a), (b) illustrate the corresponding As 3d spectra of the samples with ALD-Al2O3 and HfO2 dielectrics respectively before and after the high-k deposition, confirming the removal of As-O bonding upon ALD of these high-k layers. However, unlike the observed significant reduction of arsenic oxides, the level of Ga-O bonding remained almost unchanged. GaAs MOS capacitors were fabricated on p-type substrates with a doping concentration of 0.5-1×10 cm. A wet clean recipe was employed using a combination of HF-dip and sulfur passivation in (NH4)2S (20%). Next, 65A thick ALD-HfAlO gate dielectric was deposited at 250C, followed by TaN metal gate sputtering and patterning. The XPS analysis on the sulfide treated samples confirmed the absence of arsenic oxides as well as a significant reduction in the level of Ga-O bonding with respect to the non-treated samples. Furthermore, TEM studies revealed an abrupt highk/GaAs interface. Figure 2(a), (b) show the frequency dispersion behavior of an MOS capacitor at room temperature and 150C. It has been reported that interface states at a very small portion of the GaAs bandgap will be probed by monitoring the RT frequency dispersion behavior. Hence, performing an additional measurement at 150C is essential in order to safely conclude low midgap interface trap density (Dit). However, we observed an increase in the dispersion of the C-V curves at 150C with respect to the room temperature, implying a relatively high midgap Dit. The midgap Dit was measured to be 3-4×10 eV cm using ac-conductance method. Self-aligned E-mode n-channel GaAs MOSFETs were fabricated with ALD-Al2O3 gate dielectric, employing the same wet cleaning recipe. Source/drain (S/D) regions received a Si implant of 30keV with a dose of 1×10 cm. Dopant activation was carried out at 800C in N2 ambient. The threshold voltage and subthreshold slope were deduced to be 0.3V and ~145mV/dec from ID-VG characteristics. The maximum drive current at a gate overdrive of 2.0V for a MOSFET with a gate length of 5μm was measured to be ~16μA/μm. In summary, we have studied the chemical, physical and electrical properties of the interface between ALD-HfAlO gate dielectric and GaAs substrates. Self-aligned E-mode GaAs MOSFETs were successfully fabricated, confirming the effectiveness of the ex situ GaAs surface chemical treatment in mitigating the strong Fermi level pinning. This work was supported in part by DARPA and Micron Foundation.