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The proposed research study investigates the relationship between Bone Mineral Density (BMD) values extracted from computed tomography (CT) scans, with a primary focus on their significance in vertebral segmentation. The study includes 25 subjects spanning five age groups; the study reveals a continuous reduction in mean Hounsfield Unit (HU) values with aging, validated by statistical analysis that emphasizes the importance of these findings across different vertebral levels. The data exposes a steady decline in mean BMD values with age, ranging from 175.05 HU in the 40s to 51.8 HU in the over-80s age group, exhibiting statistically significant differences ( $\text{p} < 0.05$ ). Subgroup analysis provides granular insights into age-related variations at specific lumbar vertebrae levels by contributing valuable information to the complexities of bone health assessment. The research connects mathematics and medical imaging to improve our understanding of vertebral characteristics by introducing the Radon Transform as a fundamental tool in CT image reconstruction. These findings include both p and mean values which have the potential to revolutionize the field of bone health assessment by affecting public health policy and opening the way for more personalized and successful treatment options. This includes the earlier detection of conditions like osteoporosis and improvements in patient care.

The proliferation of battery-operated end-user electronic devices due to technological advancements, especially in medical image processing applications, demands low power consumption, high-speed operation, and efficient coding. The design of these devices is centered on the Application-Specific Integrated Circuits (ASIC), General Purpose Processors (GPP), and Field Programmable Gate Array (FPGA) frameworks. The need for low-power functional blocks arises from the growing demand for high-performance computational units that are part of high-speed processors operating at high clock frequencies. The operational speed of the processor is determined by the computational unit, which is the workhorse of high-speed processors. A novel approach to integrating Very Large-Scale Integration (VLSI) ASIC design and the concepts of low-power VLSI compatible with medical image compression was embraced in this research. The focus of this study was the design, development, and implementation of a Power Delay Product (PDP) optimized computational unit targeted for medical image compression using ASIC design flow. This stimulates the research community’s quest to develop an ideal architecture, emphasizing on minimizing power consumption and enhancing device performance for medical image processing applications. The study uses area, delay, power, PDP, and Peak Signal-to-Noise Ratio (PSNR) as performance metrics. The research work takes inspiration from this and aims to enhance the efficiency of the computational unit through minor design modifications that significantly impact performance. This research proposes to explore the trade-off of high-performance adder and multiplier designs to design an ASIC-based computational unit using low-power techniques to enhance the efficiency in power and delay. The computational unit utilized for the digital image compression process was synthesized and implemented using gpdk 45 nm standard libraries with the Genus tool of Cadence. A reduced PDP of 46.87% was observed when the image compression was performed on a medical image, along with an improved PSNR of 5.89% for the reconstructed image.

The multiply-accumulator (MAC) unit is the basic integral computational block in every digital image and digital signal processor. As the demand grows, it is essential to design these units in an efficient manner to build a successful processor. By considering this into account, a power-efficient, high-speed MAC unit is presented in this paper. The proposed MAC unit is a combination of a two-phase clocked modified sequential multiplier and a carry-save adder (CSA) followed by an accumulator register. A novel two-phase clocked modified sequential multiplier is introduced in the multiplication stage to reduce the power and computation time. For image blurring, these multiplier and adder blocks are subsequently incorporated into the MAC unit. The experimental results demonstrated that the proposed design reduced the power consumption by 52% and improved the computation time by 4% than the conventional architectures. The developed MAC unit is implemented using 180 nm standard CMOS technology using CADENCE RTL compiler, synthesized using XILINX ISE and the image blurring effect is analyzed using MATLAB.

A 2D Discrete Cosine Transform and Inverse Discrete Cosine Transform using the B.G. Lee algorithm, incorporating a signed error-tolerant adder for additions, and a signed low-power fixed-point multiplier to perform multiplications are proposed and designed in this research. A novel Application Specific Integrated Circuit hardware implementation is used for the 2D DCT/IDCT computation of each 8 × 8 image block by optimizing the input data using the concepts of pipelining. An enhanced speed in processing and optimized arithmetic computations was observed due to the eight-stage pipeline architecture. The 2D DCT/IDCT of each 8 × 8 image segment can be quickly processed in 34 clock cycles with a substantially reduced level of circuit complexity. The B.G. Lee algorithm has been implemented using signed error-tolerant adders, signed fixed-point multipliers, and shifters, reducing computational complexity, power, and area. The Cadence Genus tool synthesized the proposed architecture with gpdk-90 nm and gpdk-45 nm technology libraries. The proposed method showed a significant reduction of 31.01%, 12.17%, and 21.11% in power, area, and PDP in comparison to the existing image compression architectures. An improved PSNR of the reconstructed image was also achieved compared to existing designs.

In emerging technologies, a vital role is played by ASIC designs in processor operations. There is a necessity to develop such a processor composed of low power blocks. This paper discusses the design exploration of the fixed-point multiply-accumulate unit to achieve high-speed and low power consumption. A 2D image convolution process is developed by stacking and combining several MAC blocks. The developed MAC comprises a sequential multiplier, controller, and optimized adder units. The entering image pixels and kernel pixels are checked for similarity and accordingly isolated by the controller unit, thereby saving power by eliminating the redundant multiplications. A novel idea of reducing the additions in image filtering operations is incorporated in the design. The performance of the proposed MAC showed a 28% power reduction compared to the conventional approaches.

In the emerging trend of Graphics Processing Architecture, IEEE 754-2008 Floating point numbers are being widely used. Convolution is one of the standard operations in image processing applications, and because of its computationally intensive nature, an appropriate and efficient image processing architecture is of great need. This paper proposes a single-precision Floating Point MAC engine to accelerate the sliding window algorithm for the 2-D convolution of image. The engine uses a modified algorithm for virtual zero-padding that saves memory space, and it also provides configurable parameters to specify filter and image size. A low power multiplier with reduced dynamic power, specifically when operating on pixels and a faster increment by one circuit based on AND-EXOR gate structures, has been proposed to improve the MAC architecture. Finally, the paper shows the post-synthesis power dissipation, area estimate, and the quality comparison of the image obtained from the RTL Simulation of the proposed architecture.

The proliferation of battery-operated end-user electronic devices due to technological advancements, especially in medical image processing applications, demands low power consumption, high-speed operation, and efficient coding. The design of these devices is centered on the Application-Specific Integrated Circuits (ASIC), General Purpose Processors (GPP), and Field Programmable Gate Array (FPGA) frameworks. The need for low-power functional blocks arises from the growing demand for high-performance computational units that are part of high-speed processors operating at high clock frequencies. The operational speed of the processor is determined by the computational unit, which is the workhorse of high-speed processors. A novel approach to integrating Very Large-Scale Integration (VLSI) ASIC design and the concepts of low-power VLSI compatible with medical image compression was embraced in this research. The focus of this study was the design, development, and implementation of a Power Delay Product (PDP) optimized computational unit targeted for medical image compression using ASIC design flow. This stimulates the research community's quest to develop an ideal architecture, emphasizing on minimizing power consumption and enhancing device performance for medical image processing applications. The study uses area, delay, power, PDP, and Peak Signal-to-Noise Ratio (PSNR) as performance metrics. The research work takes inspiration from this and aims to enhance the efficiency of the computational unit through minor design modifications that significantly impact performance. This research proposes to explore the trade-off of high-performance adder and multiplier designs to design an ASIC-based computational unit using low-power techniques to enhance the efficiency in power and delay. The computational unit utilized for the digital image compression process was synthesized and implemented using gpdk 45 nm standard libraries with the Genus tool of Cadence. A reduced PDP of 46.87% was observed when the image compression was performed on a medical image, along with an improved PSNR of 5.89% for the reconstructed image. [ABSTRACT FROM AUTHOR]

Problem statement: Synthesis of new-gene combinations by genetic manipulation is one of the powerful tools in exploiting the commercial qualities of plants and animals. Hybrid performance is evaluated from extensive yield trials that are costly and time consuming. Approach: Four silkworm races belonging to two different voltine groups (two multivoltine races namely Pure Mysore and Nistari and two bivoltine races namely [C.sub.108] and [NB.sub.4][D.sub.2]) and the twelve regular and reciprocal hybrids derived from them were reared under standard laboratory condition analyzing six quantitative traits namely cocoon weight, shell weight, shell ratio, filament length, denier and renditta. The data of the pure races was analysed for the estimation of evaluation index to study the genetic divergence between the races, where as evaluation index, heterosis and overdominance effects were studied in twelve hybrid combinations. Results: Varied heterotic effects were observed for different traits for hybrid combination. Cocoon weight and shell weight has maximum heterosis over the mid parent in Pure Mysore x Nistari (27 and 42% respectively), whereas [C.sub.108] x Nistari have shown maximum shell ratio (30%) among the hybrids. The maximum filament length for heterosis was observed in the Nistari x Pure Mysore. Heterosis for cocoon weight, shell weight, shell ratio, filament length, denier and renditta based on evaluation index confirmed the above results. Conclusion: The investigation indicates that optimum level of genetic divergence between parents is necessary to obtain heterosis in [F.sub.1] generation. Key words: Evaluation index, genetic diversity, heterosis, silkworm, INTRODUCTION Synthesis of new-gene combinations by genetic manipulation is one of the powerful tools in exploiting the commercial qualities of plants and animals. The heterosis is observed when the animals [...]

The multiply-accumulator (MAC) unit is the basic integral computational block in every digital image and digital signal processor. As the demand grows, it is essential to design these units in an efficient manner to build a successful processor. By considering this into account, a power-efficient, high-speed MAC unit is presented in this paper. The proposed MAC unit is a combination of a two-phase clocked modified sequential multiplier and a carry-save adder (CSA) followed by an accumulator register. A novel two-phase clocked modified sequential multiplier is introduced in the multiplication stage to reduce the power and computation time. For image blurring, these multiplier and adder blocks are subsequently incorporated into the MAC unit. The experimental results demonstrated that the proposed design reduced the power consumption by 52% and improved the computation time by 4% than the conventional architectures. The developed MAC unit is implemented using 180nm standard CMOS technology using CADENCE RTL compiler, synthesized using XILINX ISE and the image blurring effect is analyzed using MATLAB. [ABSTRACT FROM AUTHOR]