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This paper is dedicated to the "50 Years of the Relevance Problem" - a long-neglected topic that begs attention from practical statisticians who are concerned with the problem of drawing inference from large-scale heterogeneous data., Comment: Revised (much-improved) version. The procedure (including all the datasets) is implemented in the R-package LPRelevance

Summary High-dimensional $k$-sample comparison is a common task in applications. We construct a class of easy-to-implement distribution-free tests based on new nonparametric tools and unexplored connections with spectral graph theory. The test is shown to have various desirable properties and a characteristic exploratory flavour that has practical consequences for statistical modelling. Numerical examples show that the proposed method works surprisingly well across a broad range of realistic situations.

In this chapter, the RD model is described to simulate the time kinetics of interface traps. The model uses inversion layer (cold) hole induced dissociation of Hydrogen passivated interfacial defects and defect-assisted conversion of atomic into molecular species (and reverse processes) in the gate insulator bulk during (and after) stress. The model is independently validated using DCIV measured data under DC and AC NBTI stress, from planar MOSFETs with different Nitrogen content in the gate insulator and FinFETs with different Germanium content in the channel. The process dependence is explained, and the validity of the physical mechanism and model parameters are discussed.

This paper proposes a coplanar waveguide fed multiband antenna for Wi-Fi and 5G networking applications. To obtain the desired frequencies, this proposed work used an innovative method consisting of frequency shifting strips (FSS) and a U-slot. The ANSYS HFSS software, a FEM-based electromagnetic field solver, is used to simulate the designed antenna. This planned antenna covers the 5G frequency bands of 28, 35, and 37 GHz, with a maximum gain of 11.61 dB and radiation efficiency of 92%. In the result analysis section, the simulated results are compared to the measured results to check the efficiency of the simulated design. This paper also includes a comparison of the proposed antenna performance with that of other existing antennas. This paper also includes information on antenna gain, VSWR, field distributions, bandwidth, and surface current distributions (both E and H field) about the designed antenna.

In this work, we propose a novel double quantum well (QW) high electron mobility transistor (HEMT) structure. The DC and RF performances of this proposed structure are compared with those of conventional single QW HEMT. According to this work, the peak drain current of 651 mA/mm is achieved in conventional single QW HEMT, and the peak drain current of 758 mA/mm is achieved in proposed double QW HEMT. Also, the peak transconductances related to the proposed HEMT and conventional HEMT are compared. The peak current gain cut-off frequencies of two structures are compared. Also, the peak power gain cut-off frequencies of two structures are compared. According to these comparisons by simulation studies, the proposed double QW HEMT is more electrically efficient than the conventional single QW HEMT. Therefore, this present work may be a suitable prediction for the experimental fabrication of proposed double QW HEMT in future. This work may be suitable in sensor related applications and high frequency applications.

We have entered a new era of machine learning (ML), where the most accurate algorithm with superior predictive power may not even be deployable, unless it is admissible under the regulatory constraints. This has led to great interest in developing fair, transparent and trustworthy ML methods. The purpose of this article is to introduce a new information-theoretic learning framework (admissible machine learning) and algorithmic risk-management tools (InfoGram, L-features, ALFA-testing) that can guide an analyst to redesign off-the-shelf ML methods to be regulatory compliant, while maintaining good prediction accuracy. We have illustrated our approach using several real-data examples from financial sectors, biomedical research, marketing campaigns, and the criminal justice system., Comment: Keywords: Admissible machine learning; InfoGram; L-Features; Information-theory; ALFA-testing, Algorithmic risk management; Fairness; Interpretability; COREml; FINEml

To keep up with the dominance in the field of leading semiconductor technology innovation, TSMC has announced the risk production of its most advanced 5nm CMOS logic node [1] using the full-fledged EUV and high mobility channel (HMC) FinFETs. Supporting the state of the art mobile SOC chips and HPC application needs, this 5nm technology node provides ~1.8x improvement in logic density, 15% speed gain and 30% power reduction as compared to its previous 7nm generation [1] - [2] . This paper, for the first time, brings out the detailed reliability attributes for the TSMC 5nm technology node from the device to various chip/package level reliability testing. While delivering an enhanced performance for N5, here we demonstrate the reliability benefit in terms of Bias Temperature Instability (BTI), Hot Carrier Degradation (HCD), Time dependent dielectric breakdown (TDDB) degradation modes in device level. Not only that, N5 node also delivers excellent reliability margins in chip level evaluations for SRAM and logic CPU/GPU applications. Moreover, to compete with the strictest industry reliability requirements even to the DPPM or low DPPB levels, N5 logic confirms its benefit for the automotive applications.

Negative and Positive Bias Temperature Instabilities (NBTI, PBTI) respectively in P and N channel High-K Metal Gate (HKMG) MOSFETs are modeled by trap generation (TG) and charge trapping (CT) and validated against measured data. The mechanism of TG (interface) is incorporated into TCAD and is separately validated using independent experiments. BTI kinetics is modeled at different stress bias (V G ) and temperature (T). Impacts of Nitrogen (N%) and Equivalent Oxide Thickness (EOT) scaling on the magnitude of BTI and its time, VG and T dependencies are modeled.

We present advanced FinFET characterization and circuit analysis at reduced temperatures down to 77 K. Steepened subthreshold slope enables threshold voltage $(V_{\mathrm{TH}})$ and supply voltage $(V_{\mathrm{DD}})$ scaling for $\sim 0.27\times$ power reduction without sacrificing logic switching speed. With simultaneous $V_{\mathrm{TH}}$ scaling, SRAM can operate at the same low $V_{\mathrm{DD}}$ of 0 4V. Improved gate dielectric reliability raises maximum $V_{\mathrm{DE}}$ for $gt; 70\%$ speed boost when single thread performance is needed. Taking advantage of lower Cu wire resistance at 77 K, the repeaters for global signal propagation can be redesigned for 80% energy reduction. Increased thermal conductivity of silicon at low temperature reduces self-heating and further improves power efficiency. When refrigeration power is included, net power reduction can be achieved when cooling efficiency exceeds $\sim$ 50% of Carnot limit. We present effective $V_{\mathrm{TH}}$ reduction methods for both nFET and pFET, critical for attaining high performance for cold CMOS.

In this work, we have optimized the device structure to achieve a maximum drain current of Nanoelectronic AlGaN/GaN single-heterojunction high electron mobility transistors (HEMTs) by the variations of mole fraction, doping concentration and gate length, using the SILVACO-ATLAS software tool. The drain current increases at higher aluminium mole fraction of AlGaN nano-layer. The drain current increases at higher doping concentration of AlGaN nano-layer. The drain current reduces at higher gate length of HEMTs. The conduction band engineering in terms of quantum wells is investigated in detail by involving the Bose-Einstein expression. The simulation results of this work are supported by the available previous experimental results and analytical modelling. This work will be useful to fabricate the AlGaN/GaN HEMTs experimentally for bioengineering applications.

We report positive bias temperature instability data in replacement metal gate Ge n-channel metal–oxide–semiconductor field-effect transistors with an in-situ gate stack employing an ultrathin (5 A), stable Al2O3 interlayer (IL) using ultrafast (~microseconds) characterization techniques that ensure recovery artifact-free measurements. Comparison with state-of-the-art GeO x IL is also reported besides establishing correlations between band-edge interface trap density ( ${D}_{\text {it}}$ ), mobility ( $\mu$ ), and threshold voltage ( ${V}_{T}$ ) instability. Ultrafast measure-stress-measure (UF-MSM), ultrafast measure-stress-detrap-measure (UF-MSDM), stress-induced-leakage-current (SILC), direct-current current–voltage (DCIV), split capacitance–voltage ( ${C}$ – ${V}$ ), and low-temperature full conductance techniques along with a compact model demonstrate that: 1) trap generation occurs at IL/high- ${k}$ interface during stress; 2) an increase in $\mu$ with reduction in ${D}_{\text {it}}$ does not guarantee better reliability, i.e., ${V}_{T}$ shift and $\mu$ are uncorrelated due to their dependence on separate regions of the gate stack; 3) contributions to total ${V}_{\text {T}}$ degradation from trapping and generated traps are mutually exclusive; 4) UF-MSDM is a powerful tool to estimate trap generation; and 5) ${V}_{T}$ degradation is directly proportional to high- ${k}$ thickness, varies inversely with IL thickness, and reduces with annealing.

A comprehensive modeling framework is presented to predict the time kinetics of negative bias temperature instability stress and recovery during and after dc and ac stresses and also during mixed dc–ac stress. The model uses uncorrelated contributions from the generation of interface and bulk traps and hole trapping in preexisting bulk traps. Ultrafast measured data at different stresses and recovery biases, temperature, duty cycle and frequency, as well as arbitrary time segments with dynamically varying voltage, frequency, and activity are predicted. The role of nitrogen in the gate insulator is explained. End-of-life degradation is determined under dc and ac use conditions.

A physics-based modeling framework is proposed to calculate the threshold voltage shift ( $\Delta \text{V}_{\mathrm {T}})$ in planar high-k metal gate (HKMG) n-MOSFETs for positive bias temperature instability (PBTI). Overall $\Delta \text{V}_{\mathrm { {T}}}$ is estimated using the uncorrelated contributions from the trap generation (TG) and the electron trapping subcomponents. The time evolution of $\Delta \text{V}_{\mathrm { {T}}}$ , measured using an ultrafast measure-stress-measure method during dc and ac stress and after dc stress, is predicted for different experimental conditions. The modeled TG component is verified by independent direct-current I–V method. The proposed model explains PBTI in differently processed HKMG gate stacks.

Developing algorithmic solutions to tackle the rapidly increasing variety of data types, by now, is recognized as an outstanding open problem of modern statistics and data science. But why does this issue remain difficult to solve programmatically? Is it merely a passing trend, or does it have the potential to radically change the way we build learning algorithms? Discussing these questions without falling victim to the big data hype is not an easy task. Nonetheless, an attempt will be made to better understand the core statistical issues, in a manner to which every data scientist can relate.

Degradation in planar high-k metal gate p- and n-channel MOSFETs, respectively, under negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) stress is studied using different characterization methods. Ultrafast measure stress measure (UF-MSM) method with a measurement delay of a few microseconds is used to characterize the threshold voltage shift ( $\Delta V_{T}$ ). Gated-diode or direct current IV is used to directly estimate the trap generation (TG) during BTI, after correcting for the measurement inconsistencies. BTI experiments are performed under DC stress at different stress bias ( $V_{\mathrm {G-STR}}$ ) and temperature ( ${T}$ ) values also under AC stress at different pulse duty cycle (PDC) and frequency ( ${f}$ ) values. Measured $\Delta V_{T}$ as well as TG show remarkable similarities between NBTI and PBTI stress, under both DC and AC stress. It is shown that TG dominates NBTI and PBTI degradation under both DC and AC stress.

To handle the ubiquitous problem of "dependence learning," copulas are quickly becoming a pervasive tool across a wide range of data-driven disciplines encompassing neuroscience, finance, econometrics, genomics, social science, machine learning, healthcare and many more. Copula (or connection) functions were invented in 1959 by Abe Sklar in response to a query of Maurice Frechet. After 60 years, where do we stand now? This article provides a history of the key developments and offers a unified perspective., Comment: A perspective on "60 years of Copula"

The increasing impact of self-heating effect (SHE) in complex FinFET structure is a serious reliability concern. Although the evaluation of SHE has become extremely arduous; this work proposes an in-situ layout based experimental solution to find out the precise thermal time constant (T TH ) due to SHE on advanced FinFET devices, even with the application of very pragmatic ‘circuit-like’ gate and drain input waveforms. Using this precise T TH , the accurate dynamic thermal profile is found out from SPICE simulations. Finally, the true degradations due to different reliability mechanisms are evaluated including SHE impact and successfully compared with measured FinFET silicon data.

The two key issues of modern Bayesian statistics are: (i) establishing principled approach for distilling statistical prior that is consistent with the given data from an initial believable scientific prior; and (ii) development of a consolidated Bayes-frequentist data analysis workflow that is more effective than either of the two separately. In this paper, we propose the idea of “Bayes via goodness-of-fit” as a framework for exploring these fundamental questions, in a way that is general enough to embrace almost all of the familiar probability models. Several examples, spanning application areas such as clinical trials, metrology, insurance, medicine, and ecology show the unique benefit of this new point of view as a practical data science tool.

This work presents a systematic study of the off-state drain bias time dependent dielectric breakdown (TDDB) mechanism, especially for the short channel transistors in advanced FinFET technologies. The sub-threshold leakage current was found to play a key role in determining the off-state drain bias TDDB degradation. Short channel transistors show higher electric field (E-Field) near the drain side due to increase in sub-threshold leakage current and hence, the breakdown lifetime is seen to scale with decrease in channel length. Moreover, with additional process optimizations, such as source/drain proximity push, the sub-threshold leakage current increases which results in worse off-state TDDB and shorter lifetime during practical circuit stress conditions. Also, impact of body bias on sub-threshold current is also studied in this work.

There is an overwhelmingly large literature and algorithms already available on "large-scale inference problems" based on different modeling techniques and cultures. Our primary goal in this article is not to add one more new methodology to the existing toolbox but instead (i) to clarify the mystery how these different simultaneous inference methods are connected, (ii) to provide an alternative more intuitive derivation of the formulas that leads to simpler expressions in order (iii) to develop a unified algorithm for practitioners. A detailed discussion on representation, estimation, inference, and model selection is given. Applications to a variety of real and simulated datasets show promise. We end with several future research directions.

Consider a big data multiple testing task, where, due to storage and computational bottlenecks, one is given a very large collection of p-values by splitting into manageable chunks and distributing over thousands of computer nodes. This paper is concerned with the following question: How can we find the full data multiple testing solution by operating completely independently on individual machines in parallel, without any data exchange between nodes? This version of the problem tends naturally to arise in a wide range of data-intensive science and industry applications whose methodological solution has not appeared in the literature to date; therefore, we feel it is necessary to undertake such analysis. Based on the nonparametric functional statistical viewpoint of large-scale inference, started in Mukhopadhyay (2016), this paper furnishes a new computing model that brings unexpected simplicity to the design of the algorithm which might otherwise seem daunting using classical approach and notations., Comment: Revised version

Presence of any erroneous leakage current source, due to any intrinsic or extrinsic device failure, can severely impact the 6-Transistor (6T) SRAM performance. This study introduces a ‘Pseudo-Leakage’ (PL) current source in the SRAM 6T circuit and takes a pragmatic approach to analyze the possible impact on the SRAM performance matrices which are affected by such leakage issues. All key factors such as SRAM static noise margin (SNM), cell driving current (Icell) and ‘high’ (‘1’) node voltage stability are studied in this work. Finally, the SRAM speed and the crucial SNM Initial-operation-Voltage (SNMIV) are estimated in the presence of such leakage source.

Negative Bias Temperature Instability (NBTI) is due to interface trap generation (ΔN it ) and trapping of holes in gate insulator traps (ΔN It ). However, the isolation methods and the relative dominance of ΔN it and ΔN it , time constants of ΔN it and ΔN it for stress, recovery and associated temperature (T) activation, and whether ΔN it recovers or remains permanent after stress, are widely debated. The resolution of such disputes is necessary to develop a reliable NBTI model. This work uses carefully designed measurements and simulations to resolve the aforementioned disputes. The contribution of ΔN it and ΔN it on overall threshold voltage shift (ΔN t ) is determined. Kinetics of ΔN it and ΔN it during stress and recovery, T activation and associated time constants are verified in both large and small area devices. Existing theoretical models for ΔN it and ΔN it are benchmarked and validated against DC and AC experiments. Capability of the existing models for predicting end-of-life ΔN t is demonstrated.

A comprehensive modeling framework involving mutually uncorrelated contribution from interface trap generation and hole trapping in pre-existing, process related gate insulator traps is used to study NBTI degradation in SiON and HKMG p-MOSFETs. The model can predict time evolution of degradation during DC and AC stress, time evolution of recovery after stress, impact of stress and recovery bias and temperature, and impact of several AC stress parameters such as pulse frequency, duty cycle, duration of last pulse cycle (half or full) and pulse low bias. The model can successfully explain experimental data measured using fast and ultra-fast methods in SiON and HKMG devices having different gate insulator processes. The trap generation and trapping sub components of the composite model have been verified by independent experiments. Data published by different groups are reconciled and explained. The model can successfully predict long time DC and AC stress data and has been used to determine device degradation at end of life as EOT is scaled for different HKMG devices. (C) 2014 Elsevier Ltd. All rights reserved.

The capillary flow in SU8 based microfluidic devices fabricated in SF-100 by lithographic technique has been recorded and analysed in this report. Leakage free microfluidic flow is achieved by indirect bonding between polymethyl methacrylate (PMMA) coated glass lid surface and SU8 channel substrate during hard baking. The working liquids are dyed ethylene glycol, dyed ethanol, dyed isopropyl alcohol (IPA) and dyed liquid mixture (water and IPA). The capillary flow of dyed ethylene glycol is found to be slower in each device due to higher viscosity and lower surface wettability as compared to other working liquids. Square SU8 micropillar arrays (80 μm and 120 μm of side lengths) are fabricated on the glass bottom wall surface of SU8 based microchannel. The capillary flow of any particular working liquid is observed to be faster through the square micropillars of smaller side length due to their lower surface area to volume ratio in the device. Also, the capillary flow of polar liquids is found to be faster on the microchannel surface of higher polar component of surface free energy. The above results are highly significant to control the speed of capillary flow in lab-on-a-chip systems.

Bump-hunting or mode identification is a fundamental problem that arises in almost every scientific field of data-driven discovery. Surprisingly, very few data modeling tools are available for automatic (not requiring manual case-by-base investigation), objective (not subjective), and nonparametric (not based on restrictive parametric model assumptions) mode discovery, which can scale to large data sets. This article introduces LPMode--an algorithm based on a new theory for detecting multimodality of a probability density. We apply LPMode to answer important research questions arising in various fields from environmental science, ecology, econometrics, analytical chemistry to astronomy and cancer genomics., Comment: I would like to express my sincere thanks to the Editor and the anonymous reviewers for their in-depth comments, which have greatly improved the manuscript