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The integration of a Verticle Cavity Surface-Emitting Laser (VCSEL) array and a driving Application-Specific Integrated Circuit (ASIC) in a custom optical array transmitter module (ATx) for operation in the detector front-end is constructed, assembled and tested. The ATx provides 12 parallel channels with each channel operating at 10 Gbps. The optical transmitter eye diagram passes the eye mask and the bit-error rate (BER) less than 1E-12 transmission is achieved at 10 Gbps/ch. The overall insertion loss including the radiation induced attenuation is sufficiently low to meet the proposed link budget requirement., Comment: 10 pages, 9 figures

The upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for the development of radiation tolerant, high speed and low power serializer ASIC. We have designed a phase locked loop using a commercial 0.25 um Silicon-on-Sapphire (SoS) CMOS technology. Post-layout simulation indicates that tuning range is 3.79-5.01 GHz and power consumption is 104 mW. The PLL has been submitted for fabrication. The design and simulation results are presented., Comment: 5 pages, 13 figures, Proceedings of the Topical Workshop on Electronics for Particle Physics 2009

We develop a custom Bit Error Rate test bench based on Altera's Stratix II GX transceiver signal integrity development kit, demonstrate it on point-to-point serial optical link with data rate up to 5 Gbps, and compare it with commercial stand alone tester. The 8B/10B protocol is implemented and its effects studied. A variable optical attenuator is inserted in the fibre loop to induce transmission degradation and to measure receiver sensitivity. We report comparable receiver sensitivity results using the FPGA based tester and commercial tester. The results of the FPGA also shows that there are more one-to-zero bit flips than zero-to-one bit flips at lower error rate. In 8B/10B coded transmission, there are more word errors than bit flips, and the total error rate is less than two times that of non-coded transmission. Total error rate measured complies with simulation results, according to the protocol setup., Comment: 5 pages, 8 figures, Proceedings of the Topical Workshop on Electronics for Particle Physics 2009

A number of critical active and passive components of optical links have been tested at 77 K or lower temperatures, demonstrating potential development of optical links operating inside the liquid argon time projection chamber (LArTPC) detector cryostat. A ring oscillator, individual MOSFETs, and a high speed 16:1 serializer fabricated in a commercial 0.25-um silicon-on-sapphire CMOS technology continued to function from room temperature to 4.2 K, 15 K, and 77 K respectively. Three types of laser diodes lase from room temperature to 77 K. Optical fibers and optical connectors exhibited minute attenuation changes from room temperature to 77 K., Comment: 8 pages, 10 figures

In this paper we present the cryogenic functionality of the components of data links for the Liquid Argon Time Projection Chamber (LArTPC), a potential far site detector technology of the Long-Baseline Neutrino Experiment (LBNE). We have confirmed that an LVDS driver can drive a 20-meter CAT5E twisted pair up to 1 gigabit per second at the liquid nitrogen temperature (77 K). We have verified that a commercial-off-the-shelf (COTS) serializer, a laser diode driver, laser diodes, optical fibers and connectors, and field-programming gate arrays (FPGA's) continue to function at 77 K. A variety of COTS resistors and capacitors have been tested at 77 K. All tests we have conducted show that the cryogenic digital data links for the liquid argon time projection chamber are promising., Comment: 15 pages, 9 figures

An all transistor active inductor shunt peaking structure has been used in a prototype of 8-Gbps high-speed VCSEL driver which is designed for the optical link in ATLAS liquid Argon calorimeter upgrade. The VCSEL driver is fabricated in a commercial 0.25-um Silicon-on-Sapphire (SoS) CMOS process for radiation tolerant purpose. The all transistor active inductor shunt peaking is used to overcome the bandwidth limitation from the CMOS process. The peaking structure has the same peaking effect as the passive one, but takes a small area, does not need linear resistors and can overcome the process variation by adjust the peaking strength via an external control. The design has been tapped out, and the prototype has been proofed by the preliminary electrical test results and bit error ratio test results. The driver achieves 8-Gbps data rate as simulated with the peaking. We present the all transistor active inductor shunt peaking structure, simulation and test results in this paper., Comment: 4 pages, 6 figures and 1 table, Submitted to 'Chinese Physics C'