1. Analysis and Design of Analog Integrated Circuits
135 results on '"Stephen H. Lewis"'
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2. A Time-Interleaved SAR ADC With Signal-Independent Background Timing Calibration.
3. A Two-Step ADC With Statistical Calibration.
4. Digital Background Calibration of a Split Current-Steering DAC.
5. An algorithmic ADC with greater than rail-to-rail input range and near-Vt supply.
6. Iterative Gain Enhancement in an Algorithmic ADC.
7. Background adaptive cancellation of digital switching noise in pipelined ADCs without noise sensors.
8. A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR.
9. Calibration of pipelined ADC gain and memory errors in an adaptively equalized receiver.
10. Highly programmable switched-capacitor filters using biquads with nonuniform internal clocks.
11. An Integrator-Based Pipelined ADC With Digital Calibration.
12. A Unity-Gain Buffer with Reduced Offset and Gain Error.
13. Convergence analysis of a background interstage gain calibration technique for pipelined ADCs.
14. A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology.
15. Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors.
16. A 12-bit 20-MS/s pipelined ADC with nested digital background calibration.
17. Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling.
18. A Pipelined ADC With Metastability Error Rate <10-15 Errors/Sample.
19. A Digitally Corrected 5-mW 2-MS/s SC Delta Sigma ADC in 0.25- μ m CMOS With 94-dB SFDR.
20. Prediction of the Spectrum of a Digital Delta-Sigma Modulator Followed by a Polynomial Nonlinearity.
21. A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors.
22. Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver.
23. Self-Biased Unity-Gain Buffers With Low Gain Error.
24. Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver.
25. A Level-Crossing Analog-to-Digital Converter With Triangular Dither.
26. Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA.
27. A Two-Step ADC With Statistical Calibration
28. A 1.4 V Supply CMOS Fractional Bandgap Reference.
29. A Passive Switched-Capacitor Finite-Impulse-Response Equalizer.
30. Bandwidth Mismatch and Its Correction in Time-Interleaved Analog-to-Digital Converters.
31. Digital background calibration for memory effects in pipelined analog-to-digital converters.
32. Background interstage gain calibration technique for pipelined ADCs.
33. A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration.
34. Analysis and Design of Analog Integrated Circuits
35. Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter.
36. Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers.
37. A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration.
38. Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue.
39. A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration.
40. An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration.
41. Digital Background Calibration of a Split Current-Steering DAC
42. A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD.
43. A digital background calibration technique for time-interleaved analog-to-digital converters.
44. An analog background calibration technique for time-interleaved analog-to-digital converters.
45. A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers.
46. A mixed-signal RAM decision-feedback equalizer for disk drives.
47. A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection.
48. A second-order double-sampled delta-sigma modulator using individual-level averaging.
49. A second-order double-sampled delta-sigma modulator using additive-error switching.
50. A median peak detecting analog signal processor for hard disk drive servo.
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