Search

Electronics has been dominated by silicon since half a century. Si will dominate electronics another decade, however its functionality might change from classical field-controlled currents through channels (the Field Effect Transistor FET) to quantum mechanical effects like field-controlled hopping of single electrons from a source to a drain via a quantum dot (the Single Electron Transistor SET). Due to single electron hopping, the SET is the champion of low-power consumption. This is very attractive for the expanding Internet of Things (IoT): more and more devices need batteries and plugs. Therefore, together with improved batteries, advanced computation and communication must be delivered at extremely low-power consumption. At very low temperatures, the perfect functionality of SETs has been proven for tiny metal dots [1] and larger Si islands [2]. However, large-scale use of SETs requires Room Temperature (RT) operation, which can be achieved with tiny Si dots (<4 nm) in SiO2, exactly located between source and drain with distances of ~1…2 nm allowing quantum mechanical tunneling. Manufacturability of such nanostructures is the roadblock for large-scale use of SETs. Lithography cannot deliver the feature sizes of 1…3 nm required for RT operation. Therefore, there are currently intense studies to fulfill these requirements by self-organization processes. Convincing proof of concepts have been reported [see, e.g., 3] on room temperature operation of silicon based SETs. However, the self-organization processes developed so far are not reliable enough for large-scale integration. The ion beam technique is a well-established technology in microelectronics used for doping and amorphization of semiconductors and even for ion beam synthesis of buried layers. The parameters of ion beam processing like ion flux, fluence and energy as well as the temperature and time of the subsequent thermal treatment are very well controllable. Therefore we searched for a self-organizati

The use of single electron transistors in large-scale integrated circuits promises a further boost for higher integration density and lower power consumption. However, in order to achieve single electron operation at room temperature, quantum dots (QDs) with a few nanometers in diameter and defined tunnel junctions have to be fabricated. A technological route to achieve such requirements is the fabrication of Si QDs embedded in SiO2 by phase separation of metastable SiOx (x<2). In a CMOS-compatible manner, a Si rich oxide layer is produced by ion beam irradiation through a Si/SiO2/Si stack [1]. Choosing the right thickness of the oxide layer of ~7 nm leads to the formation of QDs in the middle of the layer [2]. The position of the Si QDs formed by the subsequent phase separation can be further controlled by applying geometrical constrains to the self-assembly process. This can be achieved in two ways. Firstly, the Si concentration in the SiO2 is strongly enhanced locally by focused ion beam induced mixing. Secondly, under broad beam irradiation of pillars consisting of Si/SiO2/Si stacks, the local mixing is defined by the pillar diameter. It is predicted by 3D kinetic Monte-Carlo (kMC) simulations that a single Si QD of few nm in diameter is formed in the middle of the SiO2 layer of the pillar structure. The optimal geometries and irradiation condition for fabricating reproducible QDs are explored by means of 3DkMC using input data from dynamic 3D ion collision simulations (TRI3DYN). We will discuss the underlying principles and the mechanism of Si QD formation by ion induced directed self-assembly and present first results of focused Ne+ ion irradiations of a Si/SiO2/Si layer stack as well as Si+ broad beam irradiations of pillars. This work is part of the project IONS4SET (Horizon 2020 research and innovation program, Grant Agreement No 688072). [1] K.-H. Heinig et al., Appl. Phys. A77, 17 (2003). [2] L. Röntzsch et al., phys. stat. sol.(a) 202, R170(2005).

Large-scale patterning by spontaneous self-structuring during spinodal decomposition of metastable SiO is a very promising synthesis process of novel nanostructured Si absorbers for 3rd generation thin-film solar cells [1]. The SiO layers have been produced by different techniques, sputtering, CVD and e-beam evaporation. Spinodal decomposition has been activated by Rapid Thermal Processing (RTP, several seconds) and very Rapid Thermal Processing (vRTP, dwell time tens of msec). When the volume fraction of Si exceeds ~30% after the phase separation SiOx-->0.5SiO2+(1-0.5x)Si, then Si forms a nanowire network. Energy-Filtered Transmission Electron Microscopy (EFTEM) studies show that nanowires have diameters of a few nanometers with a narrow distribution. This is in excellent agreement with large-scale simulations based on bit-coded kinetic Monte-Carlo. There is a considerable Si band gap widening due to quantum confinement in the nanowire network. As the wire diameter coarsens with time of heat treatment like d~t0.33, the band gap of the Si nanosponge can be optimized for solar cell application. Using an atomistic pseudopotential method, the band gap of sponges have been studied. Finally it will be shown that up-scaling of the nanotechnology described above to large-scale PV cell production is under way by industrial partners.

Large-scale self-structuring by spinodal decomposition of metastable SiO is a very promising synthesis process of novel nanostructured Si absorbers for 3rd generation solar cells [1]. The SiO layers have been produced by different techniques, sputtering, CVD and e-beam evaporation. Spinodal decomposition has been activated by Rapid Thermal Processing (RTP) and laser annealing. When the volume fraction of Si exceeds ~30% after the phase separation SiOx-->0.5SiO2+(1-0.5x)Si, then Si forms a nanowire network. Energy-Filtered Transmission Electron Microscopy (EFTEM) studies show that nanowires have diameters of a few nanometers with a narrow distribution. This is in excellent agreement with large-scale simulations based on bit-coded kinetic Monte-Carlo accelerated by Massive Parallel Programming on NVIDIA graphic cards using a CUDA code. There is a considerable Si band gap widening due to quantum confinement in the nanowire network. As the wire diameter coarsens with time of heat treatment like d~t0.33, the band gap of the Si nanosponge can be optimized for solar cell application. Using an atomistic pseudopotential method, the band gaps of sponge have been studied. Finally it will be shown that up-scaling of the nanotechnology described above to large-scale PV cell production is under way by industrial partners.

Nanostructured thin-film PV materials are expected to become more and more important due to their high competitiveness in cost reduction. Assemblies composed of quantum dots and/or wires have been reported in which quantum confinement is used as a design parameter. However, there are still problems related to the low-cost fabrication of such structures, and, in case of quantum dots embedded in a dielectric matrix, to charge carrier separation. Here, we present Si nanosponge embedded in silica as a new nanostructured active PV cell material which could overcome such problems. The Si nanosponge has typical feature sizes of 2…4 nm. This is much smaller than the ~100nm of electrochemically etched porous Si, which was studied intensively several years ago. Thus, the nanosponge shows a band gap widening by quantum confinement which allows band gap engineering for optimum adjustment to the solar spectrum. Furthermore, the Si sponge/SiO2 matrix interface is electrically passive which lowers losses. And, the Si sponge is electrically percolated, resulting in an efficient charge carrier separation. Si nanosponge is expected to replace easily a-Si in thin-film PV cell production lines. The PECVD equipment will be used to deposit SiOx instead of a-Si. The Si nanosponge is formed by thermally activated spinodal decomposition of SiOx. The large glass panels of thin-film PV cells allow a low thermal budget only, therefore scanned laser processing with ms dwell times has to be used. EFTEM images of Si nanosponge formed by co-sputtering of SiOx followed by rapid thermal processing are in full agreement with atomistic simulations of the spinodal decomposition process. Electrical and optical properties measured so far are in agreement with the expectations. Studies on the morphology of sponges form by very rapid thermal processing are under way.

Light emitting field-effect transistors based on narrow layers of silicon nanocrystals (NCs) in the gate oxide were fabricated. Direct quantum mechanical electron and hole tunneling into NCs was achieved by self-alignment of NCs-interface-distances to ~2 nm. The direct tunneling reduces oxide degradation, prolongs device lifetime and increases operation speed. Self-alignment occurs during thermal treatment of ion irradiated stacks of 50 nm polycrystalline silicon/15 nm SiO2 / (001)Si substrate. An alternating voltage (ac) was applied to the gate to inject charges into the NCs. Due to injection by direct tunneling, electroluminescence extends to higher ac frequencies than reported so far.

A light emitting feld-effect transistor (LEFET) which is based on self-aligned silicon nanocrystal delta-layers in the gate oxide of a nMOSFET device with an active gate area of 20x20 µm2 is demonstrated. Two layers of Si NCs were prepared in the gate oxide close to both Si/SiO2 interfaces by ion irradiation through the 50 nm poly-Si/15 nm SiO2/(001)Si substrate LEFET stack and subsequent annealing. An AC voltage was applied to the gate in order to inject charges of both polarities in the Si NCs. AC voltage and frequency dependent electroluminescence spectra were recorded as a function of the annealing conditions.

Scalability and performance of current FLASH memories could be improved substantially by novel devices based on multi-dot floating gate MOSFETS. Until today, ten years of research effort have been devoted to Tiwari`s idea [1] to replace the poly-silicon floating-gate of FLASH memories by a layer of Si nanocrystals. Although several groups and companies developed test-devices, a breakthrough was not achieved due to two main reasons: (i) The CMOS compatible fabrication of the layer of nanocrystals remains a great challenge (monolayer of monodisperse Si nanocrystals of high density, which has to be embedded in the gate oxide at a controlled tunnel distance of a few nm above the Si channel). (ii) The retention of the test-devices did not reach the industrial standard. Here, we present a CMOS compatible bottom-up approach of a multi-dot floating-gate nonvolatile memory fabrication which is based on ion-beam mixing of Si-SiO2 interfaces [2]. By energetic Si ion irradiation through the poly-Si gate and the gate oxide into the Si substrate, a SiOx layer forms in the interface region. During post-irradiation annealing, the flat Si/SiO2 interface rebuilts rapidly by spinodal decomposition and interface area minimization. However, in the tail of the mixing profile, Si excess nucleates in the gate oxide layer forming Si nanocrystals. These nanocrystals are separated from the substrate by a few nm thin SiO2 layer which is free of Si excess. Experimental and atomistic computer simulation studies of this bottom-up approach will be presented. Electrical characteristics of devices, which were fabricated in an industrial environment, will be shown. Predictions to overcome the main drawback in view of applicability as memory devices, i.e. the data retention of only a few months at room temperature, will be discussed. [ 1] S. Tiwari et al., IEEE Int. Electron Devices Meeting Technical Digest, 521–524 (1995). [ 2] K.-H. Heinig, T. Müller, B.Sc

is not available.

iIon irradiation induced interface mixing was used to generate silicon nanoclusters at the SiO2-Si interface of metal-oxide-semiconductor (MOS) structures aiming at electronic memory applications. No particular processing issues have been encountered during integration of this technique in standard submicronic C-MOS technology. The memory properties of the fabricated structures as a function of the Si+-irradiation dose and post-irradiation temperature and time have been examined through electrical measurements of capacitors and transistors. Low-voltage operating devices that can endure more than 106 programming/erasing cycles have been successfully achieved. While excellent device uniformity and reproducibility have been observed over 6-inch wafers, more research is still required to improve charge retention and ensure the standard 10-year retention time needed for true non-volatile memory applications.

Si nanocrystals for multi-dot floating-gate memories have been produced by non-conventional ion beam synthesis (IBS). Due to ion beam mixing irradiation with 1015-1016 Si+ cm-2 at 50-100 keV through 50 nm poly-Si and 15 nm SiO2 on (001)Si results in a considerable Si excess within the oxide. At the upper and lower interfaces of the gate oxide, this ion irradiation forms a metastable SiOx (x < 2) composition. Post-irradiation RTA thermal treatment leads to phase separation into Si and SiO2. Adjacent to the recovering interfaces, narrow SiO2 zones become denuded of excess Si. More distant excess Si precipitates as Si NCs in the gate oxide. MOSFET characteristics in terms of write/erase voltage, duration of the programming time, endurance and retention have been evaluated.

Charge storage properties of 20-30 nm gate oxides implanted with Si+ ions are investigated using MOS capacitors, single transistor structures and a non-volatile memory. The observed programming window can reach several volts for programming with electric fields of about 4-7 MV/cm. The structures exhibit good retention (250°C, 280h) and the endurance (>106 w/e-cycles) considerably exceeds the typical values of present EEPROM technologies. The capability of Si implanted SiO2 films as gate dielectrics for a real non-volatile memory is demonstrated for the first time by a 256k - nvSRAM showing a programming window of larger than 1 volt.

The report includes results of hydrogen depth profiling using Nuclear Reaction Analysis (NRA) as well as 18O depth profiling using Time-of-Fligt Secondary Ion Mass Spectroscopy (ToF-SIMS) in as implanted SiO2-layers. The measured depth profiles of H and 18O, respectively, clearly show, that as-implanted SiO2-layers soak in humidity from the ambient, which significanly influences the processes of nanocluster growth in thin SiO2-layers during thermal processing of these layers.

The report describes the experimental proof of the formation of SiO2/Si-inteface near nanocrystal delta-layers in 500 nm thick silicon oxide due to interface mixing (defined displacement of matrix atoms) using Si irradiation through the SiO2 and Ge-implantation into the SiO2 without Ge deposition near the interface. Ge has been implanted for decoration of Si precipitates near the interface by Ge during thermal treatment of the ion irradiated SiO2. RBS und XTEM investigations show that inteface near Ge-nanocrystal delta-layers are formed only in the case of ion beam mixing of the SiO2/Si-interface. The results agree with theoretical predictions done by Monte-Carlo computer simulations. Furthermore, results of hydrogen depth profiling on Si-, Ge- and Sn-implanted SiO2-layers in the as implanted state using Nuclear Reaction Analysis (NRA) are reported. From H-depth profiling we conclude that in as implanted SiO2-layers a radiation defect enhanced water inward diffusion from moisture of the ambient atmosphere takes place. The absorbed H2O (H, OH) interfere the precipitation and Ostwald-Ripening of nanocrystals during thermal treatment, following the ion implantation process.

The contribution will review recent results to the fabrication and investigation of semiconductor nanoclusters (Si, Ge, Sn) embedded in SiO2 films. Due to quantum confinement effects or the large surface/volume ratio of such clusters typical dimensions of only few nanometers exhibit remarkable properties which differ to that of the bulk values. Among different fabrication techniques the ion beam synthesis offers specific advantages to realize a large density of tiny (2-4 nm) nanoclusters and to fulfil the requirements of CMOS technology. The results of presented experiments clearly indicate that the size, density and distribution of clusters are strongly influenced by the implantation and annealing conditions. Taking these influences into account it is possible to realize desired nanocluster distributions in the SiO2 layer, e.g. the fabrication of wide regions with homogeneously distributed clusters or d-like nanocluster bands in thin SiO2 films. The specific features of semiconductor nanoparticles in SiO2 films comprise an enormous potential for future opto- and microelectronics. Optoelectronics In general, group IV nanocluster containing SiO2 films can emit light in a wide wavelength region. The topic of light emission from ion beam synthesized nanoclusters is focused on recent success in extracting intensive violet/blue photo- and electroluminescence (EL) from Si-, Ge- or Sn implanted SiO2 layers which can be attributed to a specific defect formed after the IBS process. A power efficiency up to 0,5 % for EL has been established using MOS structures. Among possible applications the properties of a monolithically integrated optocoupler with ultra low power consumption will be discussed. Microelectronics Based on a FET structure with semiconductor nanocluster containing gate oxide, a new non-volatile memory cell has been designed which makes use from the charge storage ability of small quantum dots. The advantages of this memory are attributed to the features, that

Ion beam synthesis has been applied to fabricate semiconductor (Si, Ge) nanoclusters in thin gate SiO2 films for non-volatile memory applications. The cluster size (2-3 nm), the cluster density (>5x10E11 cm-2) and the short distance to the Si/SiO2 fulfill main requirements for a cluster related memory cell. The charge storage have been clearly established at MOS and transistor structures by the shift of the flatband or threshold voltage, respectively. Typical programming windows are in the order of 1-2 V and the endurance is > 10E6 w/e-cycles. Differences of Si- and Ge-cluster containing SiO2 films with respect to the retention behaviour are finally discussed.

In the last years nanoclusters attracted much attention because of their outstanding properties for the use in opto- and microelectronics. As an example nanocrystal memories are a promising approach towards new scalable non-volatile memory structures [1, 2]. Because of their low programming voltages and the direct tunneling process for charging they overcome limitations of currently used flash EEPROM technologies. The simple structure and the possible process integration with only a few more additional process steps make this type of memory a well-suited candidate for applications in embedded systems. An effective method of producing nanoclusters in SiO2 is ion beam synthesis using Ge - or Si - implantation and subsequent annealing. This method allows the precise control over the distribution as well as the number of implanted ions and complies with common silicon technology. This work is focused on the comparison of the properties of Si and Ge nanoclusters prepared by ion beam synthesis. Thin SiO2 films (20 and 30 nm,) were thermally grown on n-type (100) Si) and implanted with Ge+ (12 and 20 keV) and Si+ (6 and 12 keV) ions. Subsequently rapid thermal annealing was performed at 950°C for 30 s under a nitrogen atmosphere. Following that a poly-Si layer (300 nm) was deposited by LPCVD and subsequently doped with P+ ions. The poly-Si layer was etched to form the gate electrode of a MOS capacitor and several additional thermal treatment steps were carried out. Microstructural investigations (XTEM, RBS and XPS) of Ge clusters showed dependent on the experimental conditions either only one volume cluster band or a two band structure consisting of one cluster band near the interface SiO2/Si and one volume band. All clusters were found in the amorphous state. As an example for 30 nm SiO2 layers implanted with 20 keV Ge+ ions to a dose of 5x1015 cm-2 show a sharp cluster band with a cluster density of 3.5x1011 cm-2 ( 50 %) in a distance of about 3 nm to the interface Si

MOSFET´s with gateoxides containing nanoclusters (Si, Ge, Sn, Sb) fabricated with different techniques (implantation, LPCVD, sputtering) are a very promising approach for future memories. This contribution reports on results obtained on Ge-implanted MOS capacitors. By varying the implantation and annealing parameters the Ge depth profile and the cluster size and distribution can be controlled. The experimental results are explained by a theoretical model, which is based on TRIM calculations, rate-equation studies and 3D kinetic Monte Carlo simulations. The electrical properties of gate-SiO\sub{2} containing Ge-nanoclusters are investigated in detail with emphasis on its feasibility for memory applications.

Nanocluster memories are promising for future non-volatile memory applications. In this work thin SiO2 films were implanted with Ge+ and Si+ and annealed subsequently. Charge storage effects of the MOS capacitors have been studied through I-V and high frequency C-V measurements. Positive voltage pulses lead to a positive flatband voltage shift of the C-V curve. Detrapping by applying negative voltage pulses leads to a negative shift. The achieved programming window using 6 V / 100 ms pulses for Ge based structures is higher than that for Si (2.0 V vs. 0.2 V). However the retention times for Si based memories are longer. For dedicated process parameters microstructural investigations (RBS, XTEM) of Ge+ implanted SiO2 layers showed two bands of clusters, one near the interface SiO2/Si and one in the center of the SiO2 layer.