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Phase Change Memory (PCM) can directly connect persistent memory to main memory bus, while it achieves high read throughput and low standby power, the critical concerns are its poor write performance and limited durability. A naturally in-spired design is the hybrid memory architecture that fuses DRAM and PCM, so as to exploit the positive aspects of both types of memory. Unfortunately, existing solutions are seriously challenged by the limited main memory size, which is the primary bottleneck of in-memory computing. In this paper, we introduce a novel Content Aware Hybrid DRAM-PCM memory system framework—CAHRAM, which exploits deduplication to improve line sharing with high memory efficiency. It reduces write traffic to hybrid memory by removing unnecessary duplicate line writes, thereby further enhancing the write endurance of PCM. And it also substantially extends available free memory space by coalescing redundant lines in hybrid memory. We also design a reference-based page migration technique to minimize the access overheads caused by the performance gap between DRAM and PCM. Compared with the state-of-the-art in a hybrid memory simulator, our experiment results show that CAHRAM can achieve the highest I/O performance and the longest PCM lifetime with the competitive efficiencies in space and energy.

Offering a combination of low latency, high energy-efficiency, and flexibility, field-programmable gate arrays (FPGAs) suit applications ranging from Internet of Things (IoT) computing to artificial intelligence (AI). The conventional static random access memory (SRAM) FPGAs face severe challenges including large standby power and low logic density due to utilization of SRAM cell and MOS switch for signal routing. In response, researchers have introduced emerging non-volatile (NV) memory technologies to solve standby power issues. However, access transistors used for NV memory cell configuration still consume a large silicon area. In this article, we introduce an NV via-switch (VS) FPGA featuring fully back-end-of-line (BEOL) signal routing and front-end-of-line (FEOL) logic computing for high logic density. The VS fabricated in BEOL is constructed by two Cu atom switches (ASs) for signal routing and two a-Si/SiN/a-Si varistors for AS configuration. We demonstrate the first implementation of the VS-FPGA at 65-nm node and evaluate its performance by various basic applications. 2.6x logic density, 1.5x energy efficiency, and 1.4x operation speed are achieved in comparison with a previous complementary AS (CAS) FPGA in which one access transistor is necessary for each CAS configuration.

Memory arrays such as SRAM cells are responsible to the high-power consumption of modern digital systems. This investigation proposed an SRAM utilizing an ultra-low power cell, implemented using the 16-nm FinFET CMOS technology. Voltage supply selection of the static RAM cells is done by gating the wordline (WL) enable. In standby mode, the cell wordline is not activated, where the cell operates on a lower voltage level so that the stored bit status is still retained. On the other hand, the normal mode is activated when the wordline of the cell is enabled. Theoretical derivations, all-PVT-corner post-layout simulations, and measurement results were provided for verification of the functionality and performance. An SRAM of 1-kb capacity is designed based on the propose cell. The on-silicon measurement demonstrates 0.006832 fJ (energy/bit) at 500 MHz clock rate and 0.8 V supply.

The paper analyzes the energy consumption of an energy-independent house in two different situations, namely when the exterior insulation is installed and, respectively, in its absence. The result of the analysis was used to assess the reduction of fuel consumption and greenhouse gas emissions of the auxiliary heating system, namely a biomass boiler. The home’s heating system consists of a Stirling cogeneration system with biogas, which produces 3 kW of electricity and 9 kW of heat, and a 50 kW biomass boiler. The biomass boiler must provide the additional heat necessary to cover the consumption of the house when the Stirling engine is running and respectively ensure the coverage of the complete heat consumption of the building when the Stirling engine is in standby mode. The analysis showed that the installation of external insulation on the building walls will reduce energy consumption by 13%–16%, depending on the variation of the outside air temperature.

Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performance is proposed in this paper that minimizes the voltage drop and current contention issue prevalent in the prior art. The HPN comprises the cross-coupled PMOS and the current mirror structure to improve the standby power performance. The proposed HPLS utilizes a split-input driver as an output stage to achieve both the area and energy efficiency. In addition, the usage of a pass transistor in the pull-down network enhances the speed performance by decreasing the rise/fall times. The performance of HPLS is verified by implementing it in CMOS 180 nm technology using Cadence tool and simulated through Spectre circuit simulator. The simulation results of the HPLS reveal 9.6 ns of delay and 66.77 fJ of energy consumption for the applied input signal of 0.4 V/1 MHz with 1.8 V high supply voltage. Further, it consumes smaller static power of 0.82 nW and occupies silicon area of 204 $$\upmu $$ m $$^{2}$$ (12 $$\upmu $$ m $$\times $$ 17 $$\upmu $$ m).

A seamless mode-switch control scheme for primary side regulation flyback with capacitorless self-adaptive startup is presented in this article to increase the system stability for full-load range and reduce the area cost. Instead of traditional soft-startup, a peak current of primary side (PCPS) control scheme without off-chip capacitor is adapted during the startup process and a homologous startup modeling is built. Including the traditional pulsewidth modulation (PWM), the pulse frequency modulation (PFM), and deep pulsewidth modulation (DPWM) are adapted to reduce the standby power at utralight load. Meanwhile, a seamless control scheme is proposed to assure the continuity among the PCPS, PWM, PFM, and DPWM mode switch. The controller chip is fabricated in 0.18 μ m BCD process. The experiment results show that the startup time and overshoot voltage are, respectively, 35 ms and 4 V at 0.8 A load current, 48 ms, and 0.2 V at 0.008 A load current. The accuracy of output voltage is within ±0.98% under different input voltages and loads while the peak power efficiency of 88.52% is achieved.

Rotational speed detection is important for alternator-voltage-regulator (AVR) to starts-up and generates regulated electric power for vehicles. However, the rotational speed detection in standby mode for self-start is challenging with low loss rectifier, such as the Schottky diode. In this paper, a novel rotational speed detection method by sensing phase voltage or field voltage at specific modes is proposed to solve the issue without extra wiring or external components. The analysis of phase voltage in standby mode considering rectifier leakage current explains the challenges of conventional detection. The derivation of field voltage in standby mode with ANSYS Maxwell simulation verifies the proposed method. The experimental platform with a three-phase six-pole pairs alternator verified that the proposed method can detect rotational speed even in self-start and low speed of 200 rpm.

In this article, the effect of large double frequency capacitor voltage ripple (CVR) on harmonic performance, efficiency, and capacitor lifetime in the cascaded H-bridge low capacitance static reactive power compensator (StatCom) (LC-StatCom) is analytically determined. With insight provided by the analysis, an LC-StatCom with modular switched capacitors is proposed that provides a degree of freedom to control the CVR magnitude. The premise of the operation is to keep redundant capacitor modules in standby mode when operating with lower currents. In addition, it is shown that by distributing losses between additional dc-side switches and the main H-bridge switches, the proposed concept provides opportunities for choosing an optimal hybrid combination of semiconductor technologies. The proposed concept is evaluated using a simulated 8.5 MVA StatCom and feasibility of the proposed system is confirmed by experiments on a seven-level 0.8 kVA single-phase LC-StatCom prototype.

Due to its high modularity and scalability, the modular multilevel converter (MMC) has extensively been used in the modern industry. The low reliability of MMCs, which are consisted of tens or hundreds of vulnerable submodules (SMs), directly impacts the power supply continuity of the access systems. Redundancy and preventive maintenance are two significant measures to improve MMC reliability in operation. Therefore, this article presents a reliability model of MMCs with numerous SMs, whose lifetime follows arbitrary distribution, in redundancy strategies, such as active mode and standby mode. The lifetime of SMs is the minimum of component lifetime, which is estimated by a physics-of-failure-based lifetime estimation approach. Employing this reliability model, a reliability-centered maintenance (RCM) scheme with a minimum annual maintenance cost, is proposed to implement the dynamic decision of the maintenance intervals, quantitatively considering multistate of MMC operation. The relationship among redundancy, maintenance, and cost is further discussed in case studies. The proposed reliability model and RCM scheme provide a guideline for MMC redundancy strategy selection and maintenance decision.

Microgrids are becoming a significant aggregation of distributed energy resources (DERs) that improves the reliability and resilience of the power delivery system. Most of the early microgrid experience occurred in behind-themeter applications for installations with critical loads and significant backup power and load prioritization requirements. Very successful systems that include campus and utility applications have been operational for up to and exceeding a decade. For these early systems, available codes and standards consisted mostly of adapted device-level legacy emergency and standby power requirements. Grid interconnection and efficient, safe operating requirements were improvised via programmed computers, and the protection focus was the microgrids themselves. The larger microgrid installations often required qualified staff trained to monitor and operate the systems.

All through the life-cycle of a standby system, it is verychallenging to keep a standby unit workable.It may be fatalif the standby found non-workablewhen needed.This paper evaluates the performance of a standby systemworking under two primary constraintsby underlining the condition of the spare unit in standby mode. The first constraint is the maximum redundancy time for the standby and the second is maximum operation time for the operating unit.The standby unit failson exceeding the maximum time threshold andthereafterthe decision about its repair/replacement is subjected tothe inspection. While after surpassing the maximum operating time limit preventive maintenance is carried outfor the operating unit.To study the long-run performance or life-cycle of the system various performance indices have been analyzed usingthe theory of discrete-state continuous-time semi-Markov regenerative processes.Exponential, Rayleigh and Weibull probability distributions are used to study the system performance numerically.

The efficient heat dissipation of electronic equipment is very important, its heat dissipation performance directly determines the life of the equipment itself. A hand-held electronic communications equipment, when used in surface temperature is exorbitant, need to heat dissipation equipment efficiently, to ensure that the use of comfort in the handheld. In accordance with this requirement, this article presents a flexible composite material based on nano-efficient cooling methods that can keep the layout, through the improvement of internal thermal path, it can achieve the effective heat dissipation. The network thermal resistance method is used to analyze the heat transfer in the equipment, and the thermal analysis of the local thermal resistance is carried out. At the same time, through the modeling of electronic equipment and the analysis of finite elements, the temperature drop of the equipment after improvement is accurately judged. Finally, the device experimental performance comparison before and after the optimization of the standby mode and working mode is verified. The results show that the optimized equipment heat source temperature can be reduced by up to 8.5°C, the surface temperature of the equipment can be reduced by about 5°C~7°C, and the final control equipment in the steady standby state of the temperature of about 39±0.5°C, to ensure the comfort of use, and also improved the service life of the equipment. The efficient thermal design of electronic equipment based on flexible nanocomposites can provide a convenient and reliable cooling solution for high-heat flow density devices.

A process for establishing an Integrated Management System (IMS) for operation and maintenance of the ETRR-2 reactor is initiated. Development and application of the IMS consider the usage of a graded approach in order to commensurate the resources devoted to management system with the importance of an item/activity and the magnitude of the risks. Literatures have introduced different methods for the concept of graded approach which is very important in applying the management, safety and technical requirements. This paper provides an additional example for the methodology of applying such approach. It suggests a grading methodology and determines the considerations that need to be taken into account in grading the application of IMS requirements. The paper introduces a proposal for classification of items or activities in the ETRR-2 into four grades. Then gives a grading example of specific controls for maintenance of structures, systems and components (SSCs) in the plant and explains the management requirements appropriate for each grade. Finally, the approach is explained briefly using an application practice on the Standby Power Supply system of the plant as a case study.

Wireless sensor nodes spend most of their time in standby mode and wake up periodically to send measurement data. Typically, a radio-frequency antenna is coupled with an amplifier to provide this wake-up function; together, these two elements recognize instances of radio signal activation. Even during standby operation, the sensor node utilizes a certain base amount of energy, which can be critical when using an energy-harvesting source. In this study, we propose a novel optical approach to the wake-up function for autonomous sensor nodes, which employs a solar cell as the wake-up signal detector. A bright light flash coming from another node or a smartphone hits a solar cell and activates the sensor node. Unlike photodiodes or RF-antennas, solar cells do not require any additional energy to detect such a signal. Therefore, the proposed electrical circuit allows the sensor node to wake-up from a complete power-off state. The solar cell of the novel wake-up receiver has an area of sensitivity of 8 mm $\times10$ mm. The wake-up signal can be recognized from a maximum distance of 25 cm at a range of ambient illumination from 0 – 1600 lx with a transmitter optical power of 20 mW. In the power-off state, the power consumption of this novel design is the lowest of all existing off-the-shelf wake-up receivers: 248 pW at 0 lx and 627 nW at 1600 lx.

A Pt-functionalized hydrogen sensor was fabricated on a recessed AlGaN/GaN heterojunction platform where the thickness of the recessed AlGaN barrier layer under the Pt catalyst was 10 nm. Sensing characteristics were investigated under two different bias modes: forward and reverse bias operations. Unlike conventional diode type sensors, the recessed heterojunction sensor exhibited superior sensing characteristics under the reverse bias operation mode in comparison to the forward bias operation mode. The thin AlGaN barrier layer enhanced the field emission process under reverse bias operation, thus enabling a high response, which had another benefit of significantly lowering standby power consumption compared to the forward bias operation mode. A response of ~870 % and a response time of ~11 sec were achieved at 200°C with a standby power consumption of 0.03 W/cm2.

This paper introduces a 10T single-ended SRAM cell with high stability and low static power. The read static noise margin is augmented by using a Schmitt-trigger inverter and decoupling the storage node from the read bitline by adding one transistor. Since writing “1” is difficult in single-ended SRAM cells, using proper capacitive coupling and also extra pMOS transistor as an access transistor mitigates the problem. To evaluate read, write, and hold yields, we performed 10,000 Monto Carlo simulations in the 32-nm technology, and the results show our cell has 7.5×, 1.4×, and 1.1 × more yields than that of the conventional 6T SRAM cell. The proposed cell also has the least static power consumption. This amount is 1.5× less than the conventional 6T at the supply voltage of 0.5 V.

In low power VLSI circuit designs, power dissipation is one of the challenging issues which is associated with threshold voltage. The reduction of threshold voltage increases the subthreshold leakage current by increasing the leakage power dissipation which plays an important role in total power dissipation. Due to this leakage power issue, the devices which are operated by battery for a long time in standby mode drained out as soon. To mitigate this problem Static Random-Access Memory (SRAM) is designed with dual control stacked inverter which exploits dual control signals. The proposed dual control stacked inverter reduces the power consumption by 43.42%, 71.71% 63.83% and reduces the delay by 77.05%, 77.06%, 77.16% when compared to sleepy stack approach, sleepy keeper approach and dual stack power gating. Similarly, the proposed dual controlled stacking SRAM with low Vth reduces the power consumption by 96.7%, 95.36%, 96.69% and 33.54% when compared to the sleepy stacky approach, sleepy keeper approach, dual stack approach and dual controlled stacking. The proposed SRAM cell increases the reliability of overall System on Chip.

The article provides linearity performance parameter of junctionless nanotube TFET (JL-NT-TFET) for the application of ultra-low standby power and radio frequency ICs (RFICs). The proposed charge plasma device uses an inner gate with a similar workfunction as the outer gate electrode. The inner gate of the device provides better electrostatic controllability, increases turn-on capability. JL-NT-TFET shows the subthreshold swing of 20.5 mV decade, minimum leakage current, and higher current as compared to junctionless nanowire TFET (JL-NW-TFET). Linearity performance analyzed in terms of VIP2, VIP3, IIP3 and 1-dB compression point. Results obtained from JL-NTTFET is further compared to JL-NW-TFET. Simulation results of both the devices indicate that the JL-NT-TFET shows better linearity performance, hence it can be applied to low power high-frequency applications.

An ultralow-voltage retention SRAM (ULVR-SRAM) cell using header and footer power-switches (HFPSs) is investigated for power-gating (PG) applications. The cell can change its operational mode depending on the cell voltage ( ${V} _{\mathrm{ cell}}$ ) controlled by the HFPSs: When the ordinary supply voltage is applied, the cell can act as a high-performance SRAM cell. When ${V} _{\mathrm{ cell}}$ is reduced to an ultralow voltage, the cell can transition to the ULVR mode and dramatically reduce the leakage power without losing its data, i.e., the substantive PG can be achieved using the ULVR. The ability of leakage power reduction is enhanced by introducing the body biases that are automatically induced only during the ULVR mode. The design methodology is developed based on quasi-static noise margins, where the transistor sizes and the bias condition for ${V} _{\mathrm{ cell}}$ are determined so as to minimize the leakage power with keeping a sufficiently high noise margin in the ULVR mode. An optimally designed ULVR-SRAM cell shows excellent PG ability: The leakage power can be reduced by ~98% using the ULVR and a minimally short break-even time of $1.5\mu \text{s}$ can be achieved for the 8KB macro. The ULVR-SRAM can provide a new class of energy efficient PG architecture.