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The Single Event Upset (SEU) characterization on the partially depleted (PD) Silicon-On-Insulator (SOI) SRAMs manufactured by 0.5/0.35 μm CMOS technology has been studied by using the experimental accelerator's testing and Monte Carlo simulation. The results show that, in spite of the good consistent between the simulated data and experimental testing, one notable phenomenon is that, linear energy transfer (LET) as the input has no manifest influence on the saturation of SEU cross-section. This non-negligible trend led us to use the term ion velocity instead of LET. The characteristics of ion velocity have certainly been proved by the experiment, while the unsimilar results are found for the simulation with no any difference from the SEU cross-section. Consequently, a more straightforward calculation in the deposited energy within sensitive volume (SV) has performed by inspecting directly into the underlying mechanism of the undetected energy loss. The loss of deposited energy has been obtained in the assumption that the heavy ions strike on the hypothetical device at oblique incidence. The unexpected energy loss resulted from incident ions at oblique incidence as edge effect indicates the importance of quantifying the efficiency of energy collection with respect to the dimensions of SV, including the variance of surface area and thickness. It is illustrated that the deposited energy induced by heavy ions on the condition of changeable surface area has more sensitivity on the incident angle and ionic characterization compared with those for the SV of variable thicknesses. Moreover, it is obtained that the fractional changes of deposited energy within the SVs of different thicknesses present a saturating trend, which can be accelerated by the increment of incident angle, and this evidence would be helpful for deeply comprehending why the implicit inaccuracy of the SEU saturated cross-section happened under the metrics of LET or ion velocity. Ultimately, the dependence of deposited energy on the surface area and thickness is further explored and discussed based on the geometrical property and radial track profile. [ABSTRACT FROM AUTHOR]

Summary: As the scale of the integrated circuit increases, the distance between transistors decreases, a trend that reduces the critical charge of the sensitive nodes of the memory cell. Consequently, Static Random Access Memory cells in high radiation environments are very prone to soft errors. A novel radiation‐hardened memory cell, the Polarity Reinforcement Feature (PRF)‐18T, is proposed in this paper, which uses the polarity reinforcement feature to reduce the number of sensitive nodes in the memory cell and can entirely and effectively tolerate single event upset and double node upset. A comparison is made in this paper with DICE‐12T, Quatro‐10T, SEA‐14T, RHBD‐14T, NASA‐13T, and SCCS‐18T memory cells in a simulation environment with Semiconductor Manufacturing International Corporation 55 nm process, the supply voltage of 1.2 V, and temperature of 25°C. In comparison, the PRF‐18T proposed in this paper has the highest critical charge value, improving by more than 15× and 3.1× compared to the DICE‐12T and RHBD‐14T, respectively, and by more than 79% and 17.6% compared to the Quatro‐10T and SEA‐14T, respectively. In the high hold static noise margin comparison, the improvement over the SEA‐14T, DICE‐12T, RHBD‐14T, and Quatro‐10T is 26.7%, 3.8×, 1.5×, and 1.2×, respectively. In the write static noise margin comparison, the results were similar to the Quatro‐10T, DICE‐12T, and SEA‐14T, with a 68.5% improvement compared to the RHBD‐14T. Finally, the robustness of the proposed cell to process, voltage, and temperature variations is verified by temperature change experiments and 2000 Monte Carlo model simulations. [ABSTRACT FROM AUTHOR]

Artificial intelligence (AI) has revolutionized present-day life through automation and independent decision-making capabilities. For AI hardware implementations, the 6T-SRAM cell is a suitable candidate due to its performance edge over its counterparts. However, modern AI hardware such as neural networks (NNs) access off-chip data quite often, degrading the overall system performance. Compute-in-memory (CIM) reduces off-chip data access transactions. One CIM approach is based on the mixed-signal domain, but it suffers from limited bit precision and signal margin issues. An alternate emerging approach uses the all-digital signal domain that provides better signal margins and bit precision; however, it will be at the expense of hardware overhead. We have analyzed digital signal domain CIM silicon-verified 6T-SRAM CIM solutions, after classifying them as SRAM-based accelerators, i.e., near-memory computing (NMC), and custom SRAM-based CIM, i.e., in-memory-computing (IMC). We have focused on multiply and accumulate (MAC) as the most frequent operation in convolution neural networks (CNNs) and compared state-of-the-art implementations. Neural networks with low weight precision, i.e., <12b, show lower accuracy but higher power efficiency. An input precision of 8b achieves implementation requirements. The maximum performance reported is 7.49 TOPS at 330 MHz, while custom SRAM-based performance has shown a maximum of 5.6 GOPS at 100 MHz. The second part of this article analyzes the FinFET 6T-SRAM as one of the critical components in determining overall performance of an AI computing system. We have investigated the FinFET 6T-SRAM cell performance and limitations as dictated by the FinFET technology-specific parameters, such as sizing, threshold voltage (Vth), supply voltage (VDD), and process and environmental variations. The HD FinFET 6T-SRAM cell shows 32% lower read access time and 1.09 times better leakage power as compared with the HC cell configuration. The minimum achievable supply voltage is 600 mV without utilization of any read- or write-assist scheme for all cell configurations, while temperature variations show noise margin deviation of up to 22% of the nominal values. [ABSTRACT FROM AUTHOR]

In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the solution to the problem became a necessity for the designers. Single event upset (SEU), also known as soft error, is one of the most frequent issues to tackle in semiconductor devices. To mitigate the effect of soft error due to single-event upset, the radiation-hardening-by-design (RHBD) technique has been employed for Ge DLTFET-based SRAM cells. This technique uses RC feedback paths between the two cross-coupled inverters of an SRAM cell. The soft-error sensitivity is estimated for a conventional and RHBD-based SRAM cell design. It is found that the RHBD-based SRAM cell design is more efficient to mitigate the soft-error effect in comparison to the conventional design. The delay and stability parameters, obtained from the N-curve, of the Ge DLTFET-based SRAM cell performs better than the conventional Si TFET-based SRAM cell. There is an improvement of 305x & 850x in the static power noise margin and write trip power values of the Ge DLTFET SRAM cell with respect to the conventional Si TFET SRAM cell. [ABSTRACT FROM AUTHOR]

In this paper, a hybrid memory architecture based on a new array of SRAM and resistive random-access memory (RRAM) cells is proposed to perform in-memory computing by implementing all basic two-input Boolean functions. The SRAM array can be configured as a dual-purpose element. It can be used as an SRAM array in memory mode to keep data for high-performance application requirements. It can also be configured as a sense amplifier (SA-SRAM) for reading the contents of RRAMs and performing the in-memory computation. The circuits are designed using independent-gate FinFET (IG-FinFET), whose channel is controlled by two independent gates, increasing the design’s maneuverability. Our results indicate that the proposed SA-SRAM cells’ write energy consumption and combined word line margin (CWLM) achieve 50% and 20% improvements compared to the conventional 8T SRAM. Moreover, by benefiting from the combination of SRAM and RRAM cells in the proposed architecture, the energy consumption of our design in application areas, such as image processing, is much lower than the well-known compared in-memory architecture designs. In addition, to address security concerns, we proposed a polymorphic circuit primitive to prevent reverse engineering or integrated circuit (IC) counterfeiting. The proposed polymorphic circuit also adds more computations to accomplish complex logic operations and the proposed hybrid memory architecture.

With technology scaling, transistor sizing as well as the distance between them, is decreasing rapidly, thereby reducing the critical charge of sensitive nodes. This reduction makes SRAM cells used for aerospace applications more susceptible to radiation as it can cause single-event upsets (SEUs) and also single-event multi-node upsets (SEMNUs). This article presents an energy-efficient dual-node-upset-recoverable 12T SRAM cell for low-power aerospace applications, EDP12T, in 65-nm CMOS technology. The proposed cell mitigates SEUs as well as SEMNUs. To judge the relative performance of EDP12T, a comparative study is made between it and other radiation-hardened cells: RHM12T, QUCCE12T, QUATRO12T, RHD12T, SRRD12T, RHPD12T, RSP14T, LWS14T, SAR14T, and S8P4N16T. EDP12T can recover from SEUs induced at all the sensitive nodes and from SEMNUs that have occurred at its internal node-pair. EDP12T exhibits better write performance than most of the comparison cells, it also consumes the least energy during write mode, and lower energy than most of the comparison cells during read mode. EDP12T exhibits a $1.08\times /1.17\times /1.37\times /1.56\times /2.32\times $ higher read stability than S8P4N16T/RHPD12T/QUCCE12T/QUATRO12T/LWS14T. Additionally, EDP12T dissipates the lowest hold power among all the cells for comparison, except for RHM12T. These improvements are obtained by the proposed cell while consuming a $1.03\times /1.06\times /1.07\times /1.08\times /1.14\times /1.43\times /2.01\times $ lower area than SAR14T/RHD12T/S8P4N16T/RSP14T/LWS14T/RHPD12T/SRRD12T. However, these advantages come with a slight penalty in the read delay.

SRAM act us cache memory such as L2 and L3 in CPU and also used as interface between the CPU and DRAM. SRAM provides high operating speed and low power consumption due to not refreshing the memory content every time. It used transistor to store the data. But the cost is high and low memory capacity and low storage capacity. In order to reduce the cost, the compact (i.e.) less number of transistors based SRAM array play vital role in cost effective memory design. The main aim of this work is to design a compact SRAM memory array for low power, low area and low cost applications. Power optimization is performed by using various ways such as logical minimization using K-map, truth table reduction and Shannon’s theorem. In this work, truth table reduction scheme is used to design a compact AND gate of decoder for SRAM array. Also the compact 1 to 2 decoder and 2 to 4 decoder are used in 2x2 SRAM array and 4x4 SRAM array by using 6T SRAM cell. Also CMOS 22nm nanotechnology is used for transistor scaling scheme. From the analysis, the 6T SRAM cell based 2x2 and 4x4 SRAM array with compact decoder offers low cost, low resource utilization and low power consumption than the regular decoder based SRAM array. [ABSTRACT FROM AUTHOR]

A new modified 7T1M non-volatile SRAM cell is presented in this paper for low power applications at subthreshold voltage (very low voltage) simply by connecting the memristor directly with storage node which is acting as storage element and adding a transistor in between the two storage nodes with feedback connection gives better performance in terms of average delay, read/write operations and RSNM/WSNM. The memristor based circuits are simulated at subthreshold is a new insight and a new effort in technology made with improvement of approximately 61% and 23% of RSNM and WSNM respectively compared to existing memory cell 7T1M and power dissipation is decreased by 66% whereas read delay and write delay obtained is nominal. Moreover, It has also simulated an adjusting 6T2M and conventional 6T at subthreshold voltage i.e. VDD=0.3V to compare its stability behaviour at lower supply voltage. [ABSTRACT FROM AUTHOR]

The aerospace environment contains extremely energetic particles that trigger single-event transients (SET), leading to single-event upsets (SEU) in the memory cell. An efficient SRAM cell must be designed to tolerate soft error to withstand the extreme environment. This paper proposes a highly efficient radiation hardened-by-design 12T P-Quatro SRAM cell based on a polarity upset mechanism. The proposed cell has better writability, and WSNM is 1.08 × higher than its counterpart We-Quatro SRAM cell. The read access time of the proposed SRAM cell is 0.96 × , 0.91 × , 0.99 × , 0.98 × smaller than 6T, Quatro, We-Quatro, and NQuatro SRAM cells, and 1.01 × higher than RHD12T cell, and the write delay of the proposed SRAM is 0.93 × , 0.46 × , 0.72 × , 0.41 × , 0.47 × , less than that of 6T, Quatro, We-Quatro, RHD12T, and NQuatro respectively. 2000 Monte Carlo simulation for power dissipation and upset margin reveals that the process variation has less impact on the proposed SRAM and 1.64 × better tolerance against logic flipping. Further, for the P-Quatro, the critical charge is 41.51 fC and is 2.05 × , 1.75 × , 1.93 × , and 1.48 × greater than Quatro, We-Quatro, RHD12T, and NQuatro memory cells. We conducted an assessment using an electrical quality matrix (EQM) that takes into account all performance parameters. The findings reveal that the EQM of the proposed cell surpasses that of the 6T, Quatro, We-Quatro, RHD12T, and NQuatro SRAM cells by factors of 0.82 × , 0.35 × , 0.49 × , 0.71 × , and 0.21 × , respectively. This indicates that the proposed cell demonstrates superior electrical quality across various metrics compared to the other SRAM cell designs evaluated. • A highly efficient radiation hardened-by-design 12T P-Quatro SRAM cell based on a polarity upset mechanism. • Using NMOS transistors instead of PMOS helps reduce charge sharing in the circuit, improving critical charge and reducing soft error upset probability. • The electrical quality matrix (EQM) of the proposed cell surpasses that of the 6T, Quatro, WeQuatro, RHD12T, and NQuatro SRAM cells. [ABSTRACT FROM AUTHOR]

A novel reduced power with enhanced speed (RPES) technique for Static Random Access Memory (SRAM) topologies using Carbon Nano Tube Field Effect Transistors (CNTFETs) instead of traditional MOSFETs which is in demand for edge AI devices, energy efficient deep neural networks, smart wearable devices and high-speed era is proposed in this paper. This work reduces propagation delay and sub-threshold leakage current using RPES technique with a power supply of 0.9V. The performance and power delay product (PDP) of 6T, 8T and 10T SRAM cells is analysed for CNTFET based RPES technique at 45nm technology. Simulated results using Stanford CNTFET model shows improvement in PDP of proposed 6T SRAM cell by 66% compared to Conv6T and 27% compared to Ternary 4TSTI 6T SRAM. Conv 8T and Diff 8T are implemented using RPES technique which shows improvement by 40.9% and 74.3% respectively. Among SE10T and Diff 10T topologies, Diff 10T has better PDP when implemented using RPES technique. All SRAM cells mentioned are analyzed for various high-k dielectric materials, oxide thickness and pitch values of CNTFET and best fitting results are proposed for SRAM cells. [ABSTRACT FROM AUTHOR]

Artificial intelligence (AI) has revolutionized present-day life through automation and independent decision-making capabilities. For AI hardware implementations, the 6T-SRAM cell is a suitable candidate due to its performance edge over its counterparts. However, modern AI hardware such as neural networks (NNs) access off-chip data quite often, degrading the overall system performance. Compute-in-memory (CIM) reduces off-chip data access transactions. One CIM approach is based on the mixed-signal domain, but it suffers from limited bit precision and signal margin issues. An alternate emerging approach uses the all-digital signal domain that provides better signal margins and bit precision; however, it will be at the expense of hardware overhead. We have analyzed digital signal domain CIM silicon-verified 6T-SRAM CIM solutions, after classifying them as SRAM-based accelerators, i.e., near-memory computing (NMC), and custom SRAM-based CIM, i.e., in-memory-computing (IMC). We have focused on multiply and accumulate (MAC) as the most frequent operation in convolution neural networks (CNNs) and compared state-of-the-art implementations. Neural networks with low weight precision, i.e., th), supply voltage (VDD), and process and environmental variations. The HD FinFET 6T-SRAM cell shows 32% lower read access time and 1.09 times better leakage power as compared with the HC cell configuration. The minimum achievable supply voltage is 600 mV without utilization of any read- or write-assist scheme for all cell configurations, while temperature variations show noise margin deviation of up to 22% of the nominal values.

The use of Internet of Things (IoT) applications become dominant in many systems. Its on-chip data processing and computations are also increasing consistently. The battery enabled and low leakage memory system at subthreshold regime is a critical requirement for these IoT applications. The cache memory designed on Static Random-Access Memory (SRAM) cell with features such as low power, high speed, and process tolerance are highly important for the IoT memory system. Therefore, a process tolerant SRAM cell with low power, improved delay and better stability is presented in this research paper. The proposed cell comprises 11 transistors designed with symmetric approach for write operations and single ended circuit for read operations that exhibits an average dynamic power saving of 43.55% and 47.75% for write and 35.59% and 36.56% for read operations compared to 6 T and 8 T SRAM cells. The cell shows an improved write delay of 26.46% and 37.16% over 6 T and 8T and read delay is lowered by 50.64% and 72.90% against 6 T and 10 T cells. The symmetric design used in core latch to improve the write noise margin (WNM) by 17.78% and 6.67% whereas the single ended separate read circuit improves the Read Static Noise Margin (RSNM) by 1.88x and 0.33x compared to 6 T and 8T cells. The read power delay product and write power delay product are lower by 1.94x, 1.39x and 0.17x, 2.02x than 6 T and 8 T cells respectively. The lower variability from 5000 samples validates the robustness of the proposed cell. The simulations are carried out in Cadence virtuoso simulator tool with Generic Process Design Kit (GPDK) 45 nm technology file in this work. [ABSTRACT FROM AUTHOR]

Considerable research has considered the design of low-power and high-speed devices. Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices. Embedded static random-access memory (SRAM) units are necessary components in fast mobile computing. Traditional SRAM cells are more energy-consuming and with lower performances. The major constraints in SRAM cells are their reliability and low power. The objectives of the proposed method are to provide a high read stability, low energy consumption, and better writing abilities. A transmission gate-based multi-threshold single-ended Schmitt trigger (ST) 9T SRAM cell in a bit-interleaving structure without a write-back scheme is proposed. Herein, an ST inverter with a single bit-line design is used to attain the high read stability. A negative assist technique is applied to alter the trip voltage of the single-ended ST inverter. The multi-threshold complementary metal oxide semiconductor (MTCMOS) technique is adopted to reduce the leakage power in the proposed single-ended TGST 9T SRAM cell. The proposed system uses a combination of standard and ST inverters, which results in a large read stability. Compared with the previous ST 9T, ST 11T, 11T, 10T, and 7T SRAM cells, the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%, 42.09%, 31.60%, 12.54%, and 31.60% less energy for read operations and 73.59%, 93.95%, 92.76%, 89.23%, and 85.78% less energy for write operations, respectively. [ABSTRACT FROM AUTHOR]

Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled SRAM (QCCS) and the second one is called Sextuple Cross-Coupled SRAM (SCCS). The QCCS cell comprises four cross-coupled input-split inverters to keep stored values, and provides self-recoverability from SNUs at low cost. To improve reliability, the SCCS cell uses six cross-coupled input-split inverters to construct a large error-interceptive feedback loop and hence robustly keep stored values. The SCCS cell can self-recover from all possible SNUs and one part of DNUs; for remaining DNUs, a node-separation mechanism is used to avoid their occurrence. Simulation results demonstrate the robustness of the proposed cells. Moreover, compared with the state-of-the-art hardened cells, i.e., NASA13T, RHBD12T, We-Quatro, Zhang14T, QUCCE12T, DNUSRM, QCCM10T, QCCM12T, S4P8N, and S8P4N, the QCCS cell reduces read access time by 17%, write access time by 19%, power dissipation by 4% and silicon area overhead by 10% on average, while the SCCS cell reduces read access time by 44% as well as write access time by 13% on average at the cost of moderate increase in power dissipation and silicon area overhead. [ABSTRACT FROM AUTHOR]

Advanced CMOS technology is highly susceptible to ageing effects such as negative bias temperature instability (NBTI) and process variability. This article focuses on investigating the 'combined impact' of NBTI degradation along with the process, voltage and temperature (PVT) variations on SRAM metrics. These issues impact the performance of SRAM (Static Random Access Memory) cell in many ways but the two main dynamic metrics are critical read-stability and write-ability. The dynamic metrics can, in turn, be characterised by their static metrics, that determine the static noise margins (SNM) of SRAM. The dynamic metrics were analysed for symmetric and asymmetric NBTI degradation of two inverters of SRAM. NBTI degradations were incorporated on the pull-up transistors of SRAM cell. Furthermore, results of the correlated performance metrics are presented for varied data storage patterns in SRAM cell over its lifetime. This analysis aims to provide an insight into the effects of integrated PVT and NBTI degradation on SRAM cell performance, enabling robust designs and help designers at the early stage of design to mitigate system failure. [ABSTRACT FROM AUTHOR]

Today, a significant content of the system on chips (SOCs) is dedicated to static random access memory (SRAM) cells. Due to the stress during SRAM operation, MOSFET aging is becoming an increasingly serious problem. The manufacturing variability of the MOSFETs causes further differences in the aging of various devices. This paper presents a simulation methodology using a deep neural network (DNN) to predict the performance of SRAM cells, taking into account the impacts of fabrication variations, temperature, and aging. A dataset of four input features and six output criteria is utilized, which are derived from power consumption, power supply transient current, signal rise time, read static noise margin (RSNM), and butterfly and N-curve. The accuracy of the long short-term memory (LSTM) model in predicting the performance of SRAM cells outperformed the other models such as multilayer perceptron (MLP), one-dimensional convolutional neural network (1D-CNN), gated recurrent unit (GRU), and recurrent neural network (RNN) by 1.85 % to 1.11 %. For instance, by processing the supply current data, the LSTM model achieved 97.41 %, 97.96 %, and 97.41 % accuracy in predicting the RMS power consumption, the signal rise time, and the average power supply current of the SRAM cell, respectively. • DNN successfully predicts the aging and process variation impact on SRAM performance. • Supply current illustrates superior results in performance prediction. • LSTM DNN model outperforms MLP, RNN, 1D-CNN, and GRU, exhibiting sufficient accuracy. [ABSTRACT FROM AUTHOR]

Static Random Access Memory (SRAM) is primarily used as a memory storage element, which is susceptible to radiation-induced Single Event Upsets (SEUs). Hence, a robust SRAM bit-cell design is primarily a difficult task to address the space radiation environment. Furthermore, as the transistor’s size moves into nanometer regimes, a new challenge like Single Event Multiple Effects (SEME’s) evolved in SRAMs. SEME’s make the design of SRAM a serious challenge. In this article, a novel Radiation Hardened By Design (RHBD) SRAM bit-cell is proposed based on the polarity upset mechanism of SEUs. This work shows that the proposed RHBD14T SRAM bit-cell is SEU immune and delivers higher SEME critical charge than state-of-the-art RHBD SRAM bit-cells. The Monte Carlo (MC) simulations further show that the proposed RHBD14T SRAM delivers the lower Probability of Failure when compared to reported RHBD SRAM cells. Consequently, the proposed bit cell’s sensitive area is 128% lower with respect to the recently reported state-of-the-art RHBD RSP14T SRAM bit-cells. [ABSTRACT FROM AUTHOR]

Reducing the power consumption in VLSI circuits is a prime concern nowadays. Memory circuits play an important role in the design of electronic small power devices. Almost every digital system has memory as an important part in their design. The high speed circuits dissipate a considerable amount of power in a short time. In this paper, conventional SRAM cell is modified a little bit to reduce the dynamic power dissipation. The overall capacitance is reduced by adding a few extra transistors. Because of the fact that charging and discharging of the bit lines consume most power, 6T cell and 8T cell can be used to reduce the power by adding an extra number of transistors to the pull down path. 6T SRAM cell and 8T SRAM cells are simulated and their performance is compared in terms of power dissipation. [ABSTRACT FROM AUTHOR]