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The demand for large-area, high-quality synthesis of graphene with chemical vapor deposition (CVD) has increased for the realization of next-generation transparent and flexible optoelectronic applications. In conventional CVD processes, various synthesis parameters can strongly affect the quality of the resultant graphene. In particular, surface engineering of a copper catalyst substrate is one of the most promising pathways for achieving high-quality graphene with excellent reproducibility. For this purpose, simple wet chemical etching of a catalyst substrate without toxic fume byproducts or metal ion residues is desired. Here, we suggest a facile method for preparing a pretreated copper catalyst substrate for highly uniform, large-area CVD graphene growth. This pretreatment method involves a wet copper etchant, ammonium persulfate (APS) solution, and gentle ultrasonication (100 W), which do not produce unwanted or toxic fume byproducts during their reaction. Moreover, this approach does not leave metal ion residue on the cleaned copper substrates that serves as residual nucleation sites and leads to multilayer graphene growth. To evaluate the quality of the synthesized monolayer graphene on the cleaned copper catalyst substrates, we used various characterization techniques, such as Raman spectroscopy and sheet resistance, optical transmittance, and FET characterization.

One of the long-standing problems in the field of organic electronics is their instability in an open environment, especially their poor water resistance. For the reliable operation of organic devices, introducing an effective protection layer using organo-compatible materials and processes is highly desirable. Here, we report a facile method for the depositing of an organo-compatible superhydrophobic protection layer on organic semiconductors under ambient conditions. The protection layer exhibiting excellent water-repellent and self-cleaning properties was deposited onto organic semiconductors directly using a dip-coating process in a highly fluorinated solution with fluoroalkylsilane-coated titanium dioxide (TiO2) nanoparticles. The proposed protection layer did not damage the underlying organic semiconductors and had good resistance against mechanical-, thermal-, light-stress-, and water-based threats. The protected organic field-effect transistors exhibited more-reliable electrical properties, even when exposed to strong solvents, due to its superhydrophobicity. This study provides a practical solution with which to enhance the reliability of environmentally sensitive organic semiconductor devices in the natural environment.

The origin of negative differential resistance (NDR) and its derivative intermediate resistive states (IRSs) of nanocomposite memory systems have not been clearly analyzed for the past decade. To address this issue, we investigate the current fluctuations of organic nanocomposite memory devices with NDR and the IRSs under various temperature conditions. The 1/f noise scaling behaviors at various temperature conditions in the IRSs and telegraphic noise in NDR indicate the localized current pathways in the organic nanocomposite layers for each IRS. The clearly observed telegraphic noise with a long characteristic time in NDR at low temperature indicates that the localized current pathways for the IRSs are attributed to trapping/de-trapping at the deep trap levels in NDR. This study will be useful for the development and tuning of multi-bit storable organic nanocomposite memory device systems.

We investigated the trap-mediated electronic transport properties of pentacene/molybdenum disulphide (MoS2) p-n heterojunction devices. We observed that the hybrid p-n heterojunctions were gate-tunable and were strongly affected by trap-assisted tunnelling through the van der Waals gap at the heterojunction interfaces between MoS2 and pentacene. The pentacene/MoS2 p-n heterojunction diodes had gate-tunable high ideality factor, which resulted from trap-mediated conduction nature of devices. From the temperature-variable current-voltage measurement, a space-charge-limited conduction and a variable range hopping conduction at a low temperature were suggested as the gate-tunable charge transport characteristics of these hybrid p-n heterojunctions. Our study provides a better understanding of the trap-mediated electronic transport properties in organic/2-dimensional material hybrid heterojunction devices. [ABSTRACT FROM AUTHOR]

One of the long-standing problems in the field of organic electronics is their instability in an open environment, especially their poor water resistance. For the reliable operation of organic devices, introducing an effective protection layer using organo-compatible materials and processes is highly desirable. Here, we report a facile method for the depositing of an organo-compatible superhydrophobic protection layer on organic semiconductors under ambient conditions. The protection layer exhibiting excellent water-repellent and self-cleaning properties was deposited onto organic semiconductors directly using a dip-coating process in a highly fluorinated solution with fluoroalkylsilane-coated titanium dioxide (TiO 2 ) nanoparticles. The proposed protection layer did not damage the underlying organic semiconductors and had good resistance against mechanical-, thermal-, light-stress-, and water-based threats. The protected organic field-effect transistors exhibited more-reliable electrical properties, even when exposed to strong solvents, due to its superhydrophobicity. This study provides a practical solution with which to enhance the reliability of environmentally sensitive organic semiconductor devices in the natural environment.

Grain boundaries in a chemical vapour deposition (CVD)-grown monolayer of MoS 2 induce significant effects on the electrical and low frequency noise characteristics of the MoS 2 . Here, we investigated the electrical properties and noise characteristics of MoS 2 field effect transistors (FETs) made with CVD-grown monolayer MoS 2 . The electrical and noise characteristics of MoS 2 FETs were analysed and compared for the MoS 2 channel layers with and without grain boundaries. The grain boundary in the CVD-grown MoS 2 FETs can be the dominant noise source, and dependence of the extracted Hooge parameters on the gate voltage indicated the domination of the correlated number-mobility fluctuation at the grain boundaries. The percolative noise characteristics of the single grain regions of MoS 2 were concealed by the noise generated at the grain boundary. This study can enhance understanding of the electrical transport hindrance and significant noise generation by trapped charges at grain boundaries of the CVD-grown MoS 2 devices.

We investigated the current-voltage and noise characteristics of two-dimensional (2D) monolayer molybdenum disulfide (MoS 2 ) synthesized by chemical vapor deposition (CVD). A large number of trap states were produced during the CVD process of synthesizing MoS 2 , resulting in a disordered monolayer MoS 2 system. The interface trap density between CVD-grown MoS 2 and silicon dioxide was extracted from the McWhorter surface noise model. Notably, generation-recombination noise which is attributed to charge trap states was observed at the low carrier density regime. The relation between the temperature and resistance following the power law of a 2D inverted-random void model supports the idea that disordered CVD-grown monolayer MoS 2 can be analyzed using a percolation theory. This study can offer a viewpoint to interpret synthesized low-dimensional materials as highly disordered systems.

We report the electrical properties of synthesized large-area monolayer molybdenum disulfide (MoS2) field-effect transistors (FETs) with low-cost inkjet-printed Ag electrodes. The monolayer MoS2 film was grown by a chemical vapor deposition (CVD) method, and the top-contact Ag source/drain electrodes (S/D) were deposited onto the films using a low-cost drop-on-demand inkjet-printing process without any masks and surface treatments. The electrical characteristics of FETs were comparable to those fabricated by conventional deposition methods such as photo- or electron beam lithography. The contact properties between the S/D and the semiconductor layer were also evaluated using the Y-function method and an analysis of the output characteristic at the low drain voltage regimes. Furthermore, the electrical instability under positive gate-bias stress was studied to investigate the charge-trapping mechanism of the FETs. CVD-grown large-area monolayer MoS2 FETs with inkjet-printed contacts may represent an attractive approach for realizing large-area and low-cost thin-film electronics.

Recently, two-dimensional materials such as molybdenum disulfide (MoS2) have been extensively studied as channel materials for field effect transistors (FETs) because MoS2 has outstanding electrical properties such as a low subthreshold swing value, a high on/off ratio, and good carrier mobility. In this study, we characterized the electrical and photo-responsive properties of MoS2 FET when stacking a p-type organic copper phthalocyanine (CuPc) layer on the MoS2 surface. We observed that the threshold voltage of MoS2 FET could be controlled by stacking the CuPc layers due to a charge transfer phenomenon at the interface. Particularly, we demonstrated that CuPc/MoS2 hybrid devices exhibited high performance as a photodetector compared with the pristine MoS2 FETs, caused by more electron-hole pairs separation at the p-n interface. Furthermore, we found the optimized CuPc thickness (∼2 nm) on the MoS2 surface for the best performance as a photodetector with a photoresponsivity of ∼1.98 A W(-1), a detectivity of ∼6.11 × 10(10) Jones, and an external quantum efficiency of ∼12.57%. Our study suggests that the MoS2 vertical hybrid structure with organic material can be promising as efficient photodetecting devices and optoelectronic circuits.