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The objective of Phase III of this investigation was to demonstrate the reliability of the integrated circuits fabricated in Phase II according to the processes developed in Phase I (see Phase I and Phase II Final Development Reports for High-Reliability, Low-Cost Integrated Circuits, Contract No. N00039-76-C-0240). Devices were evaluated on the basis of a variety of life and environmental tests and the data recorded on magnetic tape for later retrieval and analysis. Computer software programs were developed to allow the data to be presented in a number of ways for evaluation and to allow the calculation of failure rates. (Author)

The objective of this research was to obtain radiation, reliability, and performance data on monolithic test structures containing MNOS memory transistors and n-p-n bipolar transistors. The data indicates that the devices performed acceptably at 100,000 rads (Si). Thin-oxide structures performed satisfactorily after exposure to 500,000 rads(Si). Thus, if these devices were combined into an EAROM memory circuit, a hardness level above 100,000 rads should result. Performance, reliability, and breakdown characteristics were measured and are consistent with parameter values that would be useful for an EAROM.

The objectives of Phase II of this investigation were to fabricate significant quantities of eight integrated circuit types using the techniques defined in Phase I (see Phase I Final Development Report for High Reliability, Low Cost Integrated Circuits), perform a preliminary reliability investigation, and formulate comparative cost data. Wafers and finished devices were processed for eight integrated-circuit types. These types included three TTL circuits (5420, 5472, 5470), one Schottky TTL circuit (54S20), three CMOS circuits (CD4012B, CD4014A, CD4027A) and one linear circuit (CA741). The preliminary reliability investigations defined potential reliability problems, which were subsequently successfully resolved, and provided preliminary data regarding activation energies and failure rates. The comparative cost analysis indicated that the cost goal of the contract can be met., See also Phase 1, AD-A039 954.

Processing techniques for fabricating CMOS LSI arrays with 1,000,000 rads (Si) total-dose radiation hardness were developed under this contract. Radiation-hardened processes for these technologies include bulk-silicon aluminum gate, bulk-silicon silicon-gate closed CMOS logic (C2L), and silicon-gate CMOS/SOS. Megarad total-dose hardness was demonstrated on several LSIs with silicon-gate technologies, such as the CDP1802 microprocessor and an 8-bit arithmetic logic unit (ALU). The total-dose and transient-radiation test results obtained with the ALU (TCS069) clearly demonstrated the advantages of combining radiation-hardened standard cell designs with radiation-hardened processing. These developments, funded under this contract, should dramatically increase the use of CMOS arrays in militaryt weapons systems and spacecraft used in interplanetary explorations. (Author)

Wafer fabrication has been completed. The control units (aluminum metallized DIC and DIP devices and trimetal devices in open DIC packages) are 90-percent complete. Thermal-shock testing of HRLC (high-reliability, low-cost) product has defined a beam-tape design problem which has necessitated the redesign of the beam tapes on all types. Life-test matrices have been run on CD4012 and CA741 to gain a preliminary insight into the failure modes to be expected in Phase III. (Author)

A digital phase-locked-loop circuit developed by The Charles Stark Draper Laboratory, Inc. and sponsored by the Air Force Avionics Laboratory, was successfully implemented on an RCA TCC 051 universal array (type number TCC 051 820). Twenty engineering prototypes were evaluated by the contracting agency and found acceptable. Additional 150 units were subsequently supplied. A market study was made of the commercial applicability of the DPLL LSI design. (Author)

The objective of this study was an evaluation of the reliability and associated failure mechanisms of complementary MOS integrated circuits using silicon-on-sapphire technology. The results of this investigation indicate that, with appropriate screening, the self-aligned Si-gate CMOS/SOS technology can provide reliability equivalent to that of the Al-gate, bulk-silicon CMOS technology. The tests were conducted on CD4007 type inverter circuits processed in two different CMOS/SOS technologies: Al-gate and self-aligned Si-gate. The test program consisted of various combinations of electrical, thermal, and mechanical stresses designed to accelerate failure mechanisms. Extensive analysis was performed on the failed arrays, and predominant failure modes were determined. Activation energies for the predominant failure mechanisms were obtained, and results used for reliability predictions for both the Al-gate and the self-aligned Si-gate technologies. Recommendations for screening procedures for CMOS/SOS devices are also included. It must be pointed out that the statistics resulting from this investigation apply only to the processes used by the manufacturers, A and B, whose parts were used for the stress-testing program. There is no intent to imply that the statistical results of this program apply to devices made by other manufacturers with similar technologies. (Author)

A tentative specification for a carbon black suitable for use with m-dinitrobenzene is given. The more efficient reduction of aromatic nitro groups by certain metals is examined. Electroless nickel solutions did not deposit nickel on Columbian HR-1670 carbon black. The low solubility of m-dinitrobenzene in water is changed only slightly by MgBr2, but is affected more by Mg(Cl104)2 and, especially, by reduction products of m-dinitrobenzene. A new titration method for measuring pore volume was tried and found unsuitable with carbon blacks. (Author)

Attempts were made to develop the best of the present laboratory-made cells into practical form, suitable for military applications, and to exploit the use of untried organic materials for the purpose of obtaining maximum usefulness from this new class of battery materials. A detailed discussion of the performance of the magnesiumdinitrobenzene cell and a summary of the capacity, shelf-life, delayed action, impedance, and temperature-dependence data is presented. The roles of C and H2O in the m-dinitrobenzene cathode and the effect of Mg efficiency upon cell performance were studied. Various cell configurations (round and flat) were evaluated to provide design criteria for optimum cell structures. A magnesium-m-dinitrobenzene dry cell with a capacity of 90 whr/lb is described. The theory concerning the effect of group type and position in a molecule and its effect on ca hode potential is presented for the aromatic nitro and nitroalkane compounds and extended to heterocyclic nitro compounds and organic anode materials. The more important classes of organic anode materials, hydrazine, and organic cathode materials, nitropyridines and nitrofurans are discussed in greater detail. (Author)

Process improvements were completed in all areas investigated. An improved method of removing photo resist was developed. A study of inorganic reagent materials as sources of semi-conductor surface contamination was completed. Conclusions concerning the concentrations of impurities and the effectiveness of various desorption techniques are included. The use of thin aluminum contacts has inhibited formation of ''purple plague''. Experiments with gold contacts were unsuccessful. The use of gold alloy wire did not materially improve the bond strength. Nailhead bonding with a smaller diameter gold wire to reduce the size of the ball met with only limited success. A program of reliability testing and analysis and studies of rmal resistance measurements form junction to ambient (T sub J-A) were completed.

Mg/Mg(ClO4)2 CuO reserve cells were characterized on high rates using a cell design previously developed. Several voltage variations, caused by the heat evolved, were noted during discharge. A research study was initiated to determine the mechanism by which the heat evolved influences the voltage behavior of the system. Shelf-life programs were initiated to study the delayed action, impedance, and capacity retention characteristics of the Mg/Mg(ClO4)2/ MnO2 and Mg/Mg(ClO4)2/CuO dry cells. Initial delayed action, impedance and capacity data are presented for the MnO2 cells.

A method is presented for testing various carbon blacks used with organic nitro-cathode materials based on the ability of the carbon black to adsorb m-dinitrobenzene from 2N magnesium perchlorate saturated with m- dinitrobenzene. The data obtained from adsorption tests and capacity tests for absorbed m-dinitrobenezene on various carbon blacks are summarized. Effects of reaction products are discussed, and adsorption-capacity tests are summarized for two carbon blacks selected as superior to others tested. A-cell-capacity test data are given. Eighteen-month storage-test results are given for AZ-10 magnesium A-cells; 3-month storage-test data are presented for AZ-21 magnesium A-cells made with various carbon blacks.

Techniques for preparing gallium-arsenide surfaces free of damage and suitable for epitaxial growth were investigated. A method of substrate preparation to be used for preliminary growth studies was introduced. Growth studies were started in a water vapor transport epitaxial system. This system was constructed specifically to evaluate the structure of epitaxial films in relation to the substrate. Design improvements to reduce contamination of epitaxial layers due to leaks and corrosion were made on the vapor hydride epitaxial system. This improved system is expected to be in operation shortly., See also AD847618, AD859334, AD855865, AD859901 and AD868577.

A third system intended for the preparation of high-resistivity GaAs was completed and put into operation. Six runs were made with iodine as the halogen transport agent for the gallium. No appraciable growth was obtained. A small amount of Zn was added to the gallium of the trichloride system. Successive runs under iden tical conditions yielded steadily decreasing hole concentrations. Variation in dopant vapor pressure yielded no commensurate change in hole concentration. Hydrogen sulfide gas diluted with hydrogen was used as n-type dopant. A technique for making Hall effect and resistivity measure ments on epitaxial GaAs layers was developed. The reflectivity method for measuring high car rier concentrations was refined.

Gallium arsenide was chosen as the semiconductor material best suited to meet the needs of high temperature operation because of its wide band gap and high electron mobility. Even though gallium arsenide has the best potential for high temperature operation, it does have a few limitations. One of these being that there are a number of major differences between elemental and compound semiconductors. A number of different devices were developed under this contract. These include: switching diodes, low-power rectifiers, medium-power rectifiers, high-power rectifiers, zener diodes, tunnel diodes, unipolar transistors, switching transistors, power transistors and solid ceramic circuits. Of these, the most successful were tunnel diodes and varactor diodes, since they are able to fulfill the requirements of some specific applications not filled by similar germanium and silicon devices.

A review of the overlay concept and a comparison of this structure with the comb type geometry is presented. The resistivities and diffusion parameters of this device were determined and successfully employed in the diffusion cycles. Photoresist techniques were developed which allow excellent definition and registration of the required photoresist patterns in the silicon dioxide; however, improvement is still required in the defining and etching of the aluminum. In the fabrication of the insulating layer, the main difficulty is one of opening the emitter oxide area after anodizing or silicon monoxide evaporation. The difficulty is inadequate ad herence of the defined photoresist to the sub strate resulting in lifting during immersion of the wafer in oxide etch. Devices with only a few percent of the emitter areas opened were fabricated and display excellent diode charac teristics. These results indicate the feasibil ity of the anodized aluminum approach to the fabrication of an overlay structure. Alternate approaches for producing the insulating layer are being considered. These include metal mask evaporation of a dielectric material only over the base metalling and the use of a second thin metal film over the anodized film, which can be defined, and will act as a mask for defining the silicon oxide.

Emphasis was placed on the fabrication of diodes with breakdown voltages in excess of 20 volts. Devices were made using both epitaxial and melt grown material. The change in material characteristics which occur during diffusion were investigated.

An investigation of the most direct and systematic approach in selecting the most promising materials for the development of higher capacity secondary batteries for space applications is reported. The experimental approach, materials, and necessary precautions required in molten salt technology are summarized. Advantages and disadvantages of the various molten salt elec trolytes considered are presented. Experimental procedures and couple materials investigated are discussed. The experimental results for the molten- salt cells investigated are presented. Data are presented for cells with fluoride, chloride and sulfate molten-salt electrolyte. Objectives and results of a ceramic separator study phase of the program are included. The design of a molten-salt secondary battery which was constructed during the course of the program is described, along with fabrication procedures of this battery. Theoretical calculation for the initial heat input versus heat output and the heat loss due to cell radiation is presented.

Two UHF high-power amplifier modules were developed, utilizing thin-film hybrid integrated circuit technology and a modular building block approach. Several functional integrated power amplifier stages were cascaded and paralleled, utilizing 3-dB quadrature couplers to achieve the high power gain and power output. The power amplifiers were designed to operate over the 225- to 400-megahertz frequency range and provide an objective power output of 80 watts (peak) power. Each functional integrated power amplifier stage utilizes a self-contained variable DC-bias circuit to achieve linear operation. This circuit provides the appropriate change in base-to-emitter forward bias at different power output levels of the RF amplifiers. The UHF power amplifier modules were designed specifically for amplitude-modulated systems where high peak envelope power is required. (Author)

A COS/MOS phase comparator was designed and breadboarded, using discrete components. When the breadboarded phase comparator was tested in a breadboarded frequency synthesizer, it showed improved performance over previous circuits. An integrated circuit (IC) version of the comparator was fabricated on a 58- by 92-mil chip. The performance of this IC was comparable to that of the breadboard circuit. A divide-by-K (K = 8) counter breadboard was constructed, using available IC's. A divide-by-N programmable counter was designed, using available IC's. An improved divide-by-R counter was designed and breadboarded. These counters met the requirements of the synthesizer system. Three voltage-controlled bipolar oscillators covering the required 225- to 400-megahertz tuning range were developed. A high-voltage bipolar loop amplifier, which eliminates the need for coarse tuning circuits in the synthesizer, was constructed and assembled. An MOS buffer amplifier was designed, breadboarded, and fabricated. It meets system requirements. (Author)

A COS/MOS phase comparator was designed and breadboarded, using discrete components. When the phase comparator was tested in a breadboarded frequency synthesizer, it showed improved performance over previous circuits. An IC layout for the comparator was completed, and preparation of masks was started for fabricating the circuit on a 63- by 70-mil chip. A divide-by-K (K = 4) counter breadboard was constructed, using available IC's. This counter met system requirements. A divide-by-N programmable counter was designed, using available IC's. This counter met system requirements. The possibility of reducing the required number of IC's from 15 to six was investigated. (Author)

The primary objective of the contract is to develop an MOS transistor capable of a power output (PEP) of 100 watts in the frequency band from 2 to 32 megahertz when operated from a 28-volt power supply. (Author), See also Interim engineering rept. no. 2, AD-862 428 and Interim engineering rept. no. 4, AD-875 393.

Developmental work on the mechanical aspects of the laminated overlay process was completed. Preferential emitter etching was incorporated into the process with emitter site size reduced to 2.5 mils on 5.5-mil centers. A process flow chart and a brief description of the process are presented. Preliminary measurements on laminated etched wafers showed good emitter-junction and collector-junction characteristics; however, beta was very low. It appears that the beta problem is associated with the seeding and epitaxial refill operations and is not inherent in the etched wafers. The feasibility of parallel packaging was demonstrated after minor changes were made in the design of the base connector. Thermal-stress measurements indicate severe thermal fatigue of solder-mounted pellets. It is expected that the use of an alloy having a higher lead content will improve this condition substantially. (Author), See also Interim engineering rept. no. 4, AD-869 503.

A COS/MOS phase comparator was designed and breadboarded, using discrete components. When the breadboarded phase comparator was tested in a breadboarded frequency synthesizer, it showed improved performance over previous circuits. An integrated circuit (IC) version of the comparator was fabricated on a 63- by 70-mil chip. The performance of this IC was comparable, with the exception of output noise ripple, to that of the breadboard circuit when external resistors were used to correct for offcenter biasing. It is believed that the increased output noise ripple is due to a leakage path in the IC. This leakage path could easily be corrected in a modified IC design. A divide-by-K (K=8) counter breadboard was constructed, using available IC's. This counter met system requirements. A divide-by-N programmable counter was designed, using available IC's. This counter met system requirements. An improved divide-by-R counter was designed and breadboarded, using three available COS/MOS IC packages and one TTL IC. It met the synthesizer system requirements. Three voltage-controlled oscillators covering the required 225 to 400 megahertz tuning range were developed. A high-voltage loop amplifier, which eliminates the need for coarse tuning circuits in the synthesizer, was constructed and assembled. (Author)

Twelve UHF high-power-amplifier modules were developed, utilizing thin-film hybrid integrated circuit technology and a modular building approach. Several functional, integrated, power-amplifier stages were cascaded and paralleled, utilizing 3-dB quadrature couplers to achieve the high power gain and output power. The power amplifiers were designed to operate over the 225- to 400-megahertz frequency range and provide a power output of 40 t0 50 watts of (CW) power. Each functional, integrated, power-amplifier stage utilized thin-film inductors, capacitors, resistors and transistor pellets mounted on a single 350-mil-square BeO substrate. These components were ultrasonically wire-bonded together forming a hybrid integrated circuit. The power amplifier stages were designed for direct insertion into a 50-ohm transmission line. The UHF power amplifier modules were designed specifically for amplitude-modulation systems where 40 to 50 watts fo peak power are required (10-watt carrier level). (Author)

The objective of the program described in this report is to develop photomasks, semiconductor processing technology, and packaging concepts to a level that is capable of fabricating transistors that will deliver 1 watt of output power at a frequency of 6.0 gigahertz. The approach that was taken to achieve this goal included: Use of a metal-grid, site-ballasted, 5-watt, 3.5-gigahertz design as a test vehicle for obtaining a 1-watt, 6.0-gigahertz device. Development of a high-temperature metal grid compatible with microwave transistor processing and having a sheet resistivity of less than 2 ohms per square. Development of a p type guard-ring structure to permit the use of the lowest resistivity for a given device breakdown voltage. Improvement of emitter ballasting techniques on microwave devices to obtain optimal device performance and reliability. Development of an arsenic emitter diffusion compatible with high-frequency transistor processing. Development of a high-frequency chip carrier to allow optimal device performance at 6.0 gigahertz. DC and RF evaluation of metal-grid devices in coaxial and stripline packages. Initial RF evaluation of metal-grid devices in a high-frequency chip carrier. (Author)

The objective of the manufacturing methods and technology measure (MMT) was to establish and demonstrate production techniques for ultraprecision integrated-circuit (IC) photomasks. The effectiveness of these techniques was to be verified by demonstrating the production capability for producing photomasks to a high degree of image accuracy. The effectiveness was to be further demonstrated by using the ultraprecision photomasks to manufacture IC's having better quality and higher yield. Engineering samples of photomask sets were manufactured and delivered to the contracting agency and to an in-house transistor wafer manufacturing area for pilot-line-production runs and evaluation of improved capabilities as the manufacturing methods and technology program progressed. This final report documents the successful accomplishment of all the goals of this MMT. (Author)

A basic change made in the processing technique to simplify and improve the process is described in detail. The mechanical processing steps, such as cavitronning, are performed presently from the collector side rather than from the emitter side. This has eliminated the need of a handle wafer, allowing the use of a shortened lamination cycle, and has resulted in more uniform electrical characteristics. Approximately 40 percent of the pellets pressed with the shortened cycle have had good electrical characteristics. A method of making collector contact after lamination is described. This greatly simplifies the processing of the base collector wafer. Only 0.7 mil of epitaxy is needed compared to more than 4 mils for a standard epitaxial pi-nu wafer with this voltage capability. An automatic cavitron alignment technique is also described. Initial results of high-current measurements on design IIIB and IIIC devices are given and indicate that emitter periphery is a more important factor in determining high-current performance than emitter area. Maximum collector current was 30 amps for the IIIB device compared to 18 amps for the IIIC device, which had 30 percent more emitter area but 40 percent less emitter periphery. (Author), See also Interim engineering rept. no. 2, AD-860 343.

Several changes were incorporated into the processing of the laminated transistor for the sake of simplification and yield improvement. These changes included: etching of the emitter structure in place of ultrasonic cutting; simplification of mechanical processing; and shortening of the lamination cycle. Several design modifications also were evaluated. Although these modified transistors had significantly higher power-dissipation capability (600 watts) and maximum-current capability (up to 30 amperes) than the smaller Design II devices fabricated previously (350 watts, 12 amperes), second-breakdown performance was not improved significantly. (Author), See also Interim engineering rept. no. 3, AD-863 005.

The goal of this program is the fabrication of 50- to 100-ampere rectifiers with a reverse breakdown voltage of 150 volts for operation at 300C ambient temperature in a transformer circuit. (Author), See also Interim technical rept. no. 5, AD-855 865.

Considerable progress was made towards the design and construction of rectifiers capable of 300C operation. A compatible metallization system, based on diffusion bonding tantalum shoes to an epitaxial GaAsP rectifier, was developed. A computer program was used to calculate temperature distributions and to optimize geometrical factors. Large-area, defect-free vapor hydride epitaxial n-type layers were grown; progress here was based on improved RCA-grown substrates, surface preparation, and the exclusion of oxygen during growth. Addition of phosphine during epitaxy improved the reverse breakdown characteristics. Spectrographic analysis suggests that silicon is always present in epitaxial layers grown in quartz apparatus but that a large fraction of the silicon is electrically inactive. The growth of a p-type GaAs layer from solution is very advantageous from the production point of view, but large-area void-free growth is difficult and proved to be the limiting factor in this program. Both phosphosilicate and alumina were shown to be compatible junction protective coatings. (Author)

Gallium arsenide substrate crystal material, grown in-house, that meets the preliminary specification of less than 10,000 dislocations per sq cm now is readily available in quantity. This crystal is sliced parallel to either a <100> plane or a <111> plane but offset 3 degrees toward the nearest <111> or <100> plane, respectively. A clean-up etch that also permits rejection of chemically polished, nonobvious, defective substrate material was introduced just before epitaxial growth. The origin of the defects is partly mechanical. Monitoring the furnace temperature established that the water-vapor transport system requires thirty minutes to reach thermal equilibrium and also that blanket gas flow during this period affects the surface character of the substrates. A new operating schedule was determined. The temperature profile of the hydride system was unstable and corrective action was taken, but epitaxial layers were only about 60 percent smooth. A detailed survey and analysis of commercial packages show that none will meet the requirements for the 300C rectifier. A modified stud package was designed and a trial lot ordered. The pellet will be bonded between two special alloy shoes. The shoe-pellet structure was designed to minimize thermal stresses resulting from CTE mismatch. The apparatus for diffusion bonding was assembled and mechanically tested. (Author)

The design, fabrication and testing of a high-power transistor suitable for single-sideband operation at 76 MHz are discussed. This transistor, designated the TA7117, is of an overlay construction and incorporates a diffused, integrated-ballast resistor, integral emitter and base leads, and internally mounted, low-conductance diode for temperature compensation. The design of a high-power, two-tone test amplifier with bias control is detailed and the test results on the final transistors are given. The TA7117 transistor has demonstrated a capability of 100 watts PEP with 9.5 dB gain at -28 dB intermodulation distortion and an efficiency of 70 percent. The design of a high-power, linear amplifier using the TA7117 transistor is discussed. This amplifier is capable of WPEP with -46 dB IMD. The combination of this driver with a TA7117 final amplifier stage demonstrates a solid state linear amplifier capability of 1 milliwatt PEP to 100 watts PEP. (Author)

The successful design and development of a 50-ampere rectifier with reverse breakdown over 150 volts, operable in a 300C ambient temperature, is described. High-operating-temperature and reverse-breakdown requirements led to the choice of gallium arsenide and gallium arsenide-phosphide as the semiconductor materials employed. The rectifier junctions were grown by vapor phase epitaxial techniques, and very-high breakdown voltage was achieved. Growth of defect-free large-area (0.175-mil diameter) junctions was a major accomplishment. A complete process for rectifier fabrication was developed, including etching, contacting, mounting, and junction coating techniques. The results of mechanical, electrical, and environmental tests are presented. (Author)

A 1-watt, 2-gigahertz device, coaxial transistor, having 6- to 7-dB power gain and 30- to 40-percent collector efficiency was developed in this program. This significant increase in UHF device performance is the result of technology developed during shallow diffusion and epitaxial material studies. The transistor is enclosed in a hermetic coaxial package, developed during the package study phase of this program. (Author)

Efforts were continued on a program to develop and fabricate an audio output power transistor and a suitable driver power transistor for sonar applications. Problems encountered in the epitaxial refill of the emitter-base overlay wafer are discussed in detail. Experiments on the glassing of high-voltage collector junctions are described which show that the problem of degradation of voltage in glassing is due to positive charge formation in the oxide-silicon nitride system. Significant improvement in breakdown voltage after glassing was realized by eliminating the thermal oxide and depositing silicon nitride directly on the base junction. Collector voltages as high as 1400 volts were observed on glassed transistors. A method of diffusing the collector contact region is also described. The characteristics of driver transistors fabricated during this interval are given and the test conditions described. These devices had a BV sub CEO (sus) greater than 400 volts.

The purpose of this contract is to design and construct a 50-ampere rectifier capable of operating at an ambient temperature of 300 C. The rectifier must be capable of withstanding a peak inverse voltage of 150 volts. Vapor-phase, epitaxial p-n junctions have been grown of gallium arsenide and gallium arsenide-phosphide alloys. Results were not always consistent, particularly on large-area rectifier pellets. Part of the problem, at least, was related to pits in the grown layers. These pits were associated with low breakdown voltage of small-area diodes, which coexist in the same region with high-breakdown, small-area diodes. No cause has been found for the formation of these pits. Rectifiers were completed and sealed using the etching, metalization, and soldering processes developed. Thermal cycling tests to 300 C were completed successfully, and high-forward-current tests encourage the conclusion that rectifiers with smaller areas than those planned originally can fulfill contract goals.

A new set of sequential single site diffusion photomasks was received and evaluated. The photomasks are suitable for fabricating devices, and diffusion runs have been started. Devices fabricated with a substantially different capacitance-versus-voltage curve were characterized at 2-gigahertz and exhibited improved performance. In the area of circuit evaluation and optimization, work has begun on a 2-gigahertz amplifier which will require no external tuning strips or bias tees. Power gain as a function of input drive was determined for typical 2-gigahertz devices. (Author)

The objective of this effort is to produce a transistor capable of delivering 50 watts of output power at 500 megahertz with 10-dB power gain and 50-percent efficiency. The objective will be achieved by using a metal-oxide-metal overlay structure employing integral leads. A proposed structure with the new device geometry is presented. Design characteristics are described. The advantages of employing metal-oxide-metal and integral lead technology are shown. Device development is detailed to illustrate the processing technology that has been performed on a small-area device employed as a test vehicle. A test metal-oxide-metal structure was fabricated, tested, and subjected to high-temperature testing. Results show that the silicon dioxide is an excellent dielectric for the formation of an MOM structure. The proposed package design is discussed and illustrated.