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Abstract Background Information security is very important in today’s digital world, especially cybersecurity. The most common requirement in securing data in all services: confidentiality, digital signature, authentication, and data integrity is generating random keys. These random keys should be tested for randomness. Hardware security is more recommended than software. Hardware security has more speed and less exposure to many attacks than software security. Software security is vulnerable to attacks like buffer overflow attacks, side-channel attacks, and Meltdown–Spectre attacks. Results In this paper, we propose an FPGA Implementation for the adaptive digital chaotic generator. This algorithm is proposed and tested before. We introduce its implementation as hardware. This algorithm needs a random number seed as input. We propose two designs. The first one has an input random number. The second one has PRNG inside. The target FPGA is Xilinx Spartan 6 xc6slx9-2-cpg196. We used MATLAB HDL Coder for the design. We propose a configurable Key block’s length. For 32 bit the maximum frequency is 15.711 MHz versus 11.635 MHz for the first and second designs respectively. The area utilization of the Number of Slice Registers is 1% versus 2%. The number of Slice Look Up Tables is 40% versus 59%. number of bonded input output blocks is 64% versus 66%. otherwise are the same for the two designs. Conclusions In this paper, we propose an efficient and configurable FPGA Design for adaptive digital chaotic key generator. Our design has another advantage of storing the output keys internally and reading them later.

Abstract Background MathWorks has provided an invaluable tool for designing and implementing FPGAs. MATLAB HDL coder serves a dual purpose, providing a quick proof of concept on the one hand and providing the g an easy-to-use platform for testing and verification on the other. It has main drawbacks over these advantages; it generates a code that is not optimized for both area and frequency. Results In this paper, we provide a technique for optimizing both area and frequency without losing the main advantages. The most affecting problem we found is loops. This paper classifies loop writing purposes into two types. The first one is preferable and introduces ease of writing a few lines instead of repeating the code. The second type is the problem that we intended to solve. Type II loop is appearing when the algorithm should perform these lines for several clock cycles. Writing it traditionally, force the synthesizer to implement all the repetitive clock cycles as repetitive hardware to be done in one clock cycle. This clock cycle is wide in time and is slow in frequency. This paper introduces an optimization technique for this problem. We compare before and after the implementation of our proposed technique. Conclusions We used Xilinx Spartan 6 XC6SLX4-2CPG196 FPGA. Our proposed technique improves the number of slice LUTs (Look Up Tables) requirement from 366 to 72%. The frequency improved from: 26.574 to 185.355 MHz. Based on that, we now recommend using MATLAB HDL coder in FPGA Design.

The rapid spread of technology and learning systems have altered the viewpoint about the lack of E-learning to the human element. The intersection of AI and education is highlighted by many technologists and researchers showing the diverse possibilities and challenges of using AI in education. However, little research addresses the potential of using AI to create an adaptive e-learning experience that brings a fully personalized experience to e-learners in architecture and urban educational fields. Building on that, we postulate that adaptive AI learning could be useful for urban online teaching and urban development Massive Open Online Courses (MOOCs), specifically as urban planners need to explore different scenarios of future city making. Therefore, the aim is to explore how educators from the architecture and urban field E-Learning stakeholders perceive AI in the creation of urban Moocs as well as other online teaching activities, as well as address the ways in which adaptive learning can be created in urban e-learning MOOCs using AI. In an attempt to answer the question, what is the current perception of educators about AI adaptivity in e-learning?To achieve this, first, we review the literature available on the topic to provide a comprehensive and inclusive look at adaptive AI learning, its potential, and its challenges. This overview informed and guided the formulation of the survey questions. Then we conducted a survey on educators in Architecture and urban fields from universities in Egypt. The unfamiliarity of the participants with AI provides us with deeper insights into perceptions of educators' AI adaptivity in online learning and MOOCs. The study develops a framework for adaptive e-learning using AI in an attempt to create more interactive and personalized e-learning experiences that can be used in different fields and for different types of learners.

This paper demonstrates an on–off keying (OOK) super-regenerative quenching transmitter operating in 402–405 MHz MICs band applications. To reduce power consumption, the transmitter is controlled by a novel digital quenching signal controller that generates a digital control signal to start transmitter operation when a baseband signal is input to the transmitter. The digital signal controller consists of an envelope detector, a comparator, and a quench timer designed using a state machine to synchronize the operation between the digital controller and the input baseband signal. The transmitter consists of a Colpitts oscillator operating in double operating frequency followed by a frequency divider by 2; this configuration reduces system area and improves phase noise and signal spectrum. The proposed transmitter is implemented using UMC 130 nm CMOS technology and a 1.2 V supply. Simulation shows that the proposed transmitter can meet MICS band mask specifications with data rates up to 1 Mbps and total power dissipation of 537 uW.