Search

Organic neuromorphic computing/sensing platforms are a promising concept for local monitoring and processing of biological signals in real time. Neuromorphic devices and sensors with low conductance for low power consumption and high conductance for low‐impedance sensing are desired. However, it has been a struggle to find materials and fabrication methods that satisfy both of these properties simultaneously in a single substrate. Here, nanofiber channels with a self‐formed ion‐blocking layer are fabricated to create organic electrochemical transistors (OECTs) that can be tailored to achieve low‐power neuromorphic computing and fast‐response sensing by transferring different amounts of electrospun nanofibers to each device. With their nanofiber architecture, the OECTs exhibit a low switching energy of 113 fJ and operate within a wide bandwidth (cut‐off frequency of 13.5 kHz), opening a new paradigm for energy‐efficient neuromorphic computing/sensing platforms in a biological environment without the leakage of personal information., Concepts of organic neuromorphic computing/sensing platforms for local monitoring and processing of biological signals in real time are presented. With a nanofiber architecture as a channel of a transistor, low‐power neuromorphic devices and wide‐bandwidth sensors are fabricated together on a single substrate without changing the materials, structures, and fabrication processes, demonstrating the future applications for neuromorphic computing/sensing platforms.

Ruthenium (Ru) and cobalt (Co) are new candidates for the replacement of physical vapor deposition tantalum (Ta) in liner materials because Ru and Co have excellent Cu-filling properties when deposited using chemical vapor deposition (CVD). Under accelerated current stressing conditions, Cu interconnects on a TaN/Co barrier showed an abrupt increase in resistance. The Cu resistance on a TaN/Ru barrier increased gradually and saturated with low deviation because voids generated randomly, and the Cu that remained on the Ru in the voids acted as shunt layers, preventing a sudden increase in resistance. Cu evolution tests on a Ru liner indicated that Cu had a strong bond with CVD Ru liner, even at high temperatures. These results suggest that Cu deposited on a TaN/Ru barrier can endure electromigration failure.

A novel inverted staggered metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with a combination of a planarized gate and an overlap/off-set at the source-gate/drain-gate structure were fabricated and characterized. While the MILC process is advantageous for fabricating inverted staggered poly-Si TFTs, MILC TFTs reveal higher leakage current than TFTs crystallized by other processes due to their high trap density of Ni contamination. Due to this drawback, the planarized gate and overlap/off-set structure were applied to inverted staggered MILC TFTs. The proposed device shows drastic suppression of leakage current and pinning phenomenon by reducing the lateral electric field and the space-charge limited current from the gate to the drain.

Low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) fabricated via metal-induced crystallization (MIC) are attractive candidates for use in active-matrix flat-panel displays. However, these exhibit a large leakage current due to the nickel silicide being trapped at the grain boundaries of the poly-Si. We reduced the leakage current of the MIC poly-Si TFTs by developing a gettering method to remove the Ni impurities using a Si getter layer and natively-formed SiO2 as the etch stop interlayer. The Ni trap state density (Nt) in the MIC poly-Si film decreased after the Ni silicide gettering, and as a result, the leakage current of the MIC poly-Si TFTs decreased. Furthermore, the leakage current of MIC poly-Si TFTs gradually decreased with additional gettering. To explain the gettering effect on MIC poly-Si TFTs, we suggest an appropriate model.

We report a novel method to reduce source and drain (S/D) resistances, and to form a lightly doped layer (LDL) of bottom-gate polycrystalline silicon (poly-Si) thin-film transistors (TFTs). For application in driving TFTs, which operate under high drain voltage condition, poly-Si TFTs are needed in order to attain reliability against hot-carriers as well as high field-effect mobility (μFE). With an additional doping on the p+ Si layer, sheet resistance on S/D was reduced by 37.5% and an LDL was introduced between the channel and drain. These results contributed to not only a lower leakage current and gate-induced drain leakage, but also high immunity of kink-effect and hot-carrier stress. Furthermore, the measured electrical characteristics exhibited a steep subthreshold slope of 190 mV/dec and high μFE of 263 cm2/Vs.

Top gate-structured thin-film transistors (TFTs) have a channel inversion region that is directly connected to the doped source/drain area. This stands in contrast with normal bottom gate-structured TFTs that have a channel inversion region on the downward facing side of the silicon layer regardless of the crystallinity. In this experiment, we fabricate a bottom gate TFT with a direct contact junction between the channel inversion layer and the doped source/drain area and subsequently analyze its electrical properties. The leakage current of direct junction structure is 7.4 times higher than indirect junction structure (indirect junction has 2.5 $\times 10^{-13}$ A of leakage current and direct junction has 1.85 $\times 10^{-12}$ A of leakage current). And we calculate the variation in the specific contact resistance according to differences in the intrinsic silicon thickness in order to confirm the effect that the intrinsic silicon thickness has on the bottom gate direct/indirect contact structure.

Recently, Cu interconnect and low-k materials have been applied to reduce the interconnect resistive-capacitive delay issue. However, as the process node size is reduced to a few nanometers, high leakage currents appear through the dielectric under high electric fields. Therefore, issues of Cu diffusion at the interface between the dielectric and the capping layer have been reported. This study investigated interfacial adhesion energy change at the film level between dielectric (low-k, tetraethyl orthosilicate (TEOS)) and capping layer (SiCN, SiN) taking into account the correlation between interfacial adhesion energy and interconnect reliability. In the capping layer/low-k interface, when low-k is applied to the top layer, it shows high interfacial adhesion energy (> 34.31 ± 3.49 J/m2) due to the presence of an O-rich thin layer. But when low-k is applied to the bottom layer, due to the Si C bond, it shows low interfacial adhesion energy ( 32.54 ± 1.97 J/m2) regardless of the stacking order and CMP process. It clearly shows that low-k dielectrics will affect the deterioration of the interfacial adhesion energy and O-rich layer will greatly improve the interfacial adhesion energy in dielectric/capping layers.

In this paper, the electrical properties of bottom-gate (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) by NiSi2 seed-induced lateral crystallization (SILC) and its applications are presented. Sequential lateral solidification (SLS), which is one of crystallization methods, is known to have poor electrical properties of TFTs with BG structures due to problems induced by laser. Therefore, the laser method cannot be used to well-developed production line of amorphous-Si (a-Si) TFT, resulting in large initial investment cost to change fabrication procedures. On the other hand, the BG poly-Si TFT by SILC (SILC-BGPS TFT) has basically compatible process flows with that of the a-Si TFT. The SILC-BGPS TFT exhibited threshold voltage of -3.9 V, steep subthreshold slope of 130 mV/dec, a high field-effect mobility of 129 cm2/Vs , and Ion/Ioff ratio of ~106.

Nickel silicide is main issue in Polycrystalline silicon Thin Film Transistor (TFT) which is made by Metal Induced Lateral Crystallization (MILC) method. This Nickel silicide acts as a defect center, and this defect is one of the biggest reason of the high leakage current. In this research, we fabricated polycrystalline TFTs with novel method called Edge Cut (EC). With this new fabrication method, we assumed that nickel silicide at the edge of the channel region is reduced. Electrical properties are measured and trap state density also calculated using Levinson & Proano method.

Successive breakdown (BD) has recently been observed during the back end of line (BEOL) process as the technology nodes progress. For gate dielectrics, successive BD is caused by randomly generated bond breakages of the dielectrics, whereas successive BD in inter-metal dielectrics has not been sufficiently investigated. In this work, it is confirmed that the successive BD in the BEOL is occurred by Cu metallic filaments using a facile measurement of the temperature coefficient of resistance. The Cu metallic filaments that consist of Cu atoms mediate the uncorrelated bond breakages. The time-dependent dielectric BD lifetime is improved under the bipolar stress compared to the DC and unipolar stresses. This behavior occurs because the polarity switch during the bipolar stress interferes with the formation of stable filaments due to the occurrence of Cu atom-to-ion conversion. Understanding these phenomena can lead to practical and improved projections for future technology nodes.

We developed a method to compact the glass sheets of a flat-panel displays that use metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs), and the effects of thermal stress on the fabricated devices were compared against those of a bare-glass device. The glass substrate was exposed to a temperature of 650 °C for 40 h in order to suppress the glass shrinkage to 0.01 ppm, which suitable for a MILC poly-Si TFT process. The compressive strain that originates from glass shrinkage generally increases the size of the micro-cracks and the vacancies, and as a result, most of the electrical parameters of a bare glass device (such as the on-current, off-current, field-effect mobility, subthreshold slope, and threshold voltage) had a higher level of degradation than those of the device with the compacted glass. The increase in the on-current and the field-effect hole mobility under the compressive strain for poly-Si TFTs showed a similar behavior to that of single-crystalline-silicon (c-Si) TFTs under compressive strain. However, the increase in the off-current was the converse of that of strained c-Si TFT.

In this work, we investigated a novel mechanism of polycrystalline-silicon (poly-Si) grown on tempered glass and the stability under various bias-stress effects in the performance of poly-Si thin-film transistors (TFT) fabricated on tempered glass and compared with the poly-Si TFT on bare glass. The glass shrinkage, mask misaligned width, and thermal strain of the tempered glass were 0.01 ppm, 0.9 μm, and 26.1 MPa. The compressively tensioned bare glass showed a suppression of the crystallization rate showing a small grains, whereas the tempered glass showed high crystallization rate showing a large grains. The thermal substrate stress effect on the poly-Si TFT showed serious reliability degradation, while the poly-Si TFT on tempered glass showed stable driving characteristics on the gate and hot-carrier bias stress. The better stability is due to the smooth surface and non microcracks of poly-Si on tempered glass, which is about 1.5 nm that is much smaller than that (5 nm) of a poly-Si on bare glass.

We report on a method to fabricate high-performance bottom-gate poly-Si (BGPS) thin-film transistors (TFTs) with a four-mask process via self-aligned (SA) NiSi2 seed-induced lateral crystallization (SILC). Previously, the BGPS TFT crystallized by SILC was reported to have high electrical performance with a simple process. However, this approach still requires an additional mask for lateral crystallization, making the process more complicated and expensive. In this letter, by using the SA-SILC method, only a few NiSi2 seeds reach the intrinsic Si surface through the side edges of the etch stopper and then crystallize the channel. This SA-SILC enables low metal contamination by a few seeds in the channel, shorter annealing time due to reduced length for SILC, and a simple four-mask process. The SA-SILC BGPS TFTs exhibited a steep subthreshold slope of 0.16 Vdecade $^{\mathrm { {-1}}}$ , a high field-effect mobility of 230 cm $^{2}\text{V}^{-1}\text{s}^{-1}$ , and kink-free output characteristics.

High-performance poly-Si thin-film transistors (poly-Si TFTs) with metal-induced laterally crystallized (MILC) poly-Si channel and high- $k$ ZrTiO4 (ZTO) gate dielectric are shown for the first time. The MILC poly-Si and ZTO dielectric showed smooth interface ( $\sim 1.8$ nm) with a low interfacial layer and 4.1 nm of effective-oxide thickness. The electrical performance of MILC poly-Si TFT with ZTO exhibited low threshold voltage of −0.5 V, steep subthreshold slope of 0.25 V/decade, high $I_{\mathrm{{\scriptscriptstyle ON}}}/I_{\mathrm{{\scriptscriptstyle OFF}}}$ of $1.8\times 10^{7}$ , and high field-effect mobility of 250 cm2/Vs. These characteristics correspond to the best performance of the poly-Si TFTs with high- $k$ gate dielectric reported so far. Moreover, the driving current and field-effect mobility of poly-Si TFT with ZTO gate dielectric were ten times higher than that of poly-Si TFT with deposited-SiO2 gate dielectric.

A compressively stressed polycrystalline-silicon (poly-Si) thin-film transistor (TFT) was successfully demonstrated on a tensile stressed glass substrate. The layer of a-Si:H/bare glass was annealed for 45 h with a sharp annealing and a slow cooled condition in order to form compressive strain on the a-Si:H film. Then, the a-Si:H was crystallized by NiSi2 seed-induced lateral crystallization having (110) preferred texture, and the top-gated TFT was fabricated. The electrical properties were excellent comparing with the strain-free poly-Si TFT, and especially the field-effect mobility increased 9.3 times higher.

We fabricated polysilicon thin-film transistors (TFTs) using a retrograde-mask process (RMP) showing high electrical performance, planar geometry, and stable driving characteristics. The electrical performance of RMP polysilicon TFT was compared with conventional metal-induced laterally crystallized (MILC) polysilicon TFTs. The fabrication process changed the masking steps of the conventional pattern, but did not require an additional mask. It was found that the conventional MILC poly-Si TFT typically showed a hump current, and had a serious reliability problem due to the NiSi2 contamination at the corner edges and geometry effect. One the other hand, an RMP poly-Si TFT improved the hump and the TFT’s reliability due to the absent of NiSi2 at the edges and the large effective channel length and width.

An ultrathin channel of poly-Si thin-film transistors with a quasi-lightly doped drain (Q-LDD) structure, which reduces the kink current considerably, have been proposed and fabricated. The doping concentration on the poly-Si channel was adjusted by the different thickness between source–drain and LDD region. The proposed Q-LDD shows advantages of using a thin channel and a thin-gate insulator, comparing with the conventional fabrication process of LDD using a thick oxide side walls. The gate-induced drain leakage currents were successfully suppressed without sacrifice of the ON-current and threshold voltage. Moreover, the kink effect also reduced.

The development of ferroelectric random-access memory (FeRAM) technology with control of grain boundaries would result in a breakthrough for new nonvolatile memory devices. The excellent piezoelectric and electrical properties of bulk ferroelectrics are degraded when the ferroelectric is processed into thin films because the grain boundaries then form randomly. Controlling the nature of nucleation and growth are the keys to achieving a good crystalline thin-film. However, the sought after high-quality ferroelectric thin-film has so far been thought to be impossible to make, and research has been restricted to atomic-layer deposition which is extremely expensive and has poor reproducibility. Here we demonstrate a novel epitaxial-like growth technique to achieve extremely uniform and large rectangular-shaped grains in thin-film ferroelectrics by dividing the nucleation and growth phases. With this technique, it is possible to achieve 100-μm large uniform grains, even made available on Si, which is large enough to fabricate a field-effect transistor in each grain. The electrical and reliability test results, including endurance and retention test results, were superior to other FeRAMs reported so far and thus the results presented here constitute the first step toward the development of FeRAM using epitaxial-like ferroelectric thin-films.

Excimer laser annealing (ELA) is known to be the most common crystallization technology for the fabrication of low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) in the mass production industry. This technology, however, cannot be applied to bottom-gate (BG) TFTs, which are well developed for the liquid–crystal display (LCD) back-planes, because strong laser energy of ELA can seriously damage the other layers. Here, we propose a novel high-performance BG poly-Si TFT using Ni silicide seed-induced lateral crystallization (SILC). The SILC technology renders it possible to ensure low damage in the layers, smooth surface, and longitudinal large grains in the channel. It was observed that the electrical properties exhibited a steep subthreshold slope of 110 mV/dec, high field-effect mobility of 304 cm2/Vsec, high I on/I off ratio of 5.9 × 107, and a low threshold voltage of −3.9 V.

Realizing a low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) with sub-kT/q subthreshold slope (SS) is significantly important to the development of next generation active-matrix organic-light emitting diode displays. This is the first time a sub-kT/q SS (31.44 mV/dec) incorporated with a LTPS-TFT with polycrystalline-Pb(Zr,Ti)O3 (PZT)/ZrTiO4 (ZTO) gate dielectrics has been demonstrated. The sub-kT/q SS was observed in the weak inversion region at −0.5 V showing ultra-low operating voltage with the highest mobility (250.5 cm2/Vsec) reported so far. In addition, the reliability of DC negative bias stress, hot carrier stress and self-heating stress in LTPS-TFT with negative capacitance was investigated for the first time. It was found that the self-heating stress showed accelerated SS degradation due to the PZT Curie temperature.

The development of ferroelectric random-access memory (FeRAM) technology with control of grain boundaries would result in a breakthrough for new nonvolatile memory devices. The excellent piezoelectric and electrical properties of bulk ferroelectrics are degraded when the ferroelectric is processed into thin films because the grain boundaries then form randomly. Controlling the nature of nucleation and growth are the keys to achieving a good crystalline thin-film. However, the sought after high-quality ferroelectric thin-film has so far been thought to be impossible to make, and research has been restricted to atomic-layer deposition which is extremely expensive and has poor reproducibility. Here we demonstrate a novel epitaxial-like growth technique to achieve extremely uniform and large rectangular-shaped grains in thin-film ferroelectrics by dividing the nucleation and growth phases. With this technique, it is possible to achieve 100-μm large uniform grains, even made available on Si, which is large enough to fabricate a field-effect transistor in each grain. The electrical and reliability test results, including endurance and retention test results, were superior to other FeRAMs reported so far and thus the results presented here constitute the first step toward the development of FeRAM using epitaxial-like ferroelectric thin-films.

Mucin is an important physical barrier against enteric pathogens. VvpE is an elastase encoded by Gram-negative bacterium Vibrio vulnificus; however, the functional role of VvpE in intestinal mucin (Muc) production is yet to be elucidated. The recombinant protein (r) VvpE significantly reduced the level of Muc2 in human mucus-secreting HT29-MTX cells. The repression of Muc2 induced by rVvpE was highly susceptible to the knockdown of intelectin-1b (ITLN) and sequestration of cholesterol by methyl-β-cyclodextrin. We found that rVvpE induces the recruitment of NADPH oxidase 2 and neutrophil cytosolic factor 1 into the membrane lipid rafts coupled with ITLN to facilitate the production of reactive oxygen species (ROS). The bacterial signaling of rVvpE through ROS production is uniquely mediated by the phosphorylation of ERK, which was downregulated by the silencing of the PKCδ. Moreover, rVvpE induced region-specific methylation in the Muc2 promoter to promote the transcriptional repression of Muc2. In two mouse models of V. vulnificus infection, the mutation of the vvpE gene from V. vulnificus exhibited an increased survival rate and maintained the level of Muc2 expression in intestine. These results demonstrate that VvpE inhibits Muc2 expression by hypermethylation via lipid raft-mediated ROS signaling in the intestinal epithelial cells.

Being able to control grain boundaries during the phase transformation when processing a ferroelectric thin-film is crucial for the successful development of practical multibit ferroelectric memory. A novel development of ferroelectric thin-film crystallization processing for realizing epitaxial-like single crystals via artificial nucleation by Pt-seeding is reported here. Dividing the nucleation and growth mechanism by Pt-seeding, it is possible to obtain large and uniform rectangular-shaped ferroelectric grains, large enough to fabricate a field-effect transistor (FET) in the inside of the crystal grain. The fabricated ferroelectric FET, Pt/Pb(Zr,Ti)O3/ZrTiO4/Si, showed a large memory window (∼2.2 V), a low operation voltage (∼6 V), and an ultra-fast program/erase speed (∼10−6 s). Moreover, there was no degradation after 1015 cycles of bipolar fatigue testing and the sample even showed a long retention time after 1 yr. All of these characteristics correspond to the best performance among all types of fe...

A ferroelectric-flash (F-flash) memory cells having a metal-ferroelectric-nitride-oxynitride-silicon structure are demonstrated, and the ferroelectric materials were perovskite-dominated Pb(Zr,Ti)O3 (PZT) crystallized by Pt gate electrode. The PZT thin-film as a blocking layer improves electrical and memorial performance where programming and erasing mechanism are different from the metal-ferroelectric-insulator-semiconductor device or the conventional silicon-oxide-nitride-oxide-silicon device. F-flash cells exhibit not only the excellent electrical transistor performance, having 442.7 cm2 V−1 s−1 of field-effect mobility, 190 mV dec−1 of substhreshold slope, and 8 × 105 on/off drain current ratio, but also a high reliable memory characteristics, having a large memory window (6.5 V), low-operating voltage (0 to −5 V), faster P/E switching speed (50/500 μs), long retention time (>10 years), and excellent fatigue P/E cycle (>105) due to the boosting effect, amplification effect, and energy band distortion of nitride from the large polarization. All these characteristics correspond to the best performances among conventional flash cells reported so far.