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This book has significant value to all level of students both undergraduates as well as, postgraduate students, researchers, and engineers in the field of radio-frequency integrated circuit (RFIC) design. This book provides comprehensive understanding state-of-the-art for RF design specifically radio frequency (RF) power amplifier design. It covers overview of 5G technology, fundamental of power amplifier, design implementation of 5G power amplifier, schematic design, layout and simulation results with an in-depth illustrative discussions and up-to-date references. It is useful as a reference and essential book for high-frequency circuit designers in both academia and industry.

This paper proposes the design of a very low-dropout (LDO) voltage regulator in 0.18-mm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results show that the proposed LDO is capable to operate from a supply voltage of 1.7-2.0 V with a low dropout voltage of 19.3 mV at a maximum 50 mA load current to regulate output voltage 1.5 V. The active chip is 2.96 mm2 in size. The performance of the proposed LDO is suitable to enhance power management for system on chip (SoC) applications.

This paper describes the design topology of two-stage ultra-low power low noise amplifier (LNA) using the forward body bias technique for wireless sensor network (WSN) application. The proposed des...

This paper describes the design topology of a ultra-low power low noise amplifier (LNA) for wireless sensor network (WSN) application. The proposed design of ultra-low power 2.4 GHz CMOS LNA is implemented using 0.13-μm Silterra technology. The LNA benefits of low power from forward body bias technique for first and second stages. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The simulation results show that the total power consumed is only 0.45 mW at low supply voltage of 0.55 V. The power consumption is decreased about 36% as compared with the previous work. A gain of 15.1 dB, noise figure (NF) of 5.9 dB and input third order intercept point (IIP3) of -2 dBm are achieved. The input return loss (S11) and the output return loss (S22) is -17.6 dB and -12.3 dB, respectively. Meanwhile, the calculated figure of merit (FOM) is 7.19 mW-1.

A low-dropout (LDO) voltage regulator is the main component used in the majority of portable electronic application since it is used as power management unit in those applications. In this paper, a LDO regulator for the power management integrated circuit in 0.18-µm CMOS technology using Cadence software is presented. The error amplifier of the proposed LDO employed seven transistors for current mirror. Meanwhile, the PMOS transistor is used as a pass element transistor to control the voltage variation. The resistors are used as a feedback network circuit while the capacitor is used to minimise the variation of output voltage. The simulation results show that the proposed design provides a 2.41 V constant output voltage for the supply voltage ranges of 2.55 V to 3.55 V. The dropout voltage of 140 mV is achieved with 1.48 mW power consumption. The line regulation is 1.0 mV/V and the load regulation is 0.41 mV/A, while the layout of the proposed regulator is 27 µm x 34 µm.

This paper presents a design of 3.1-6.0 GHz CMOS ultra-wideband low noise amplifier (UWB LNA) with forward body bias technique for wireless applications. The UWB LNA is designed and simulated using 0.13-μm technology in Cadence software. The proposed UWB LNA consists of two stage common-source (CS) amplifiers with a forward body bias technique. A source degenerated inductor is used at the first stage to achieve a wideband input matching and high linearity. At the second stage, a shunt-peaking inductor is employed to enhance gain at higher frequency. The simulation results indicate that the proposed UWB LNA achieves a power gain (S21) of 10 dB, an input return loss (S11) is less than −5 dB, a minimum noise figure (NF) of 8.5 dB in the frequency range of 3.1- 6.0 GHz with power dissipation of 17.2 mW. The linearity analysis shows a 1 dB compression point (P1dB) of −9 dBm and the third-order intermodulation intercept points (IIP3) of 4 dBm are achieved. The proposed UWB LNA’s layout is 0.68 mm2.

This paper presents the design and development of an IoT-based electrical conductivity system for measuring paddy soil nutrients. Relationship between electrical conductivity (EC) and the influence of soil temperature in precision farming will be discussed. In this work, the EC algorithm was modelled and verified using MATLAB and realized on Node MCU (ESP8266) microcontroller. Results showed that the measured data from the developed system is closed to the calibration solution conductivity that is 1.413mS/cm and 12.88mS/cm. It is also noted that the recorded electrical conductivity value increases with temperature.

Objects such as vehicles are considered one of challenging obstruction on the road and very little attention has been made to address its significance on the wireless signal. As such, this paper validates the impact of vehicle obstruction on signal propagation using received signal strength indicator (RSSI) based on the wireless channel measurements of realistic environmental obstruction at 2.4 GHz frequency band. Low mobility IEEE 802.15.4 XBee S2C compliant device which is designed to collect received signal power was used and these devices were deployed at area congested with cars. The channel measurements were conducted on LOS car parking area with two scenarios; single-sided and double-sided vehicle obstruction which mimics the obstruction of metal objects. The effect of existing vehicle on the signal propagation is demonstrated based on RSSI and RMSE. The attenuation profile of vehicular obstruction on wireless signal is modeled and compared with large-scale propagation models. Results show that metal object significantly reduce transmission range and signal power. The findings may incite for future implementation of cooperative deployment program and internet of things (IoT) applications in vehicle-to-infrastructure (V2I) and vehicle-to-vehicle (V2V) communication.

This paper presents a pseudo-differential transconductor circuit. Operational Transconductance Amplifier (OTA) is a standout amongst the most functional and major circuit elements within the analog and mixed-signal circuit style. It is additionally one of the more intricate cells to plan. Due to the rising performance of new generation MOS transistors, the complexity of integrated circuit is continuously increasing with time. The reduction in component sizing is one of the main reasons for integrating millions of transistors into a single chip. There is a great demand for battery powered equipment like a laptop, wireless communication, and implantable devices. In all these devices, it is essential to maintain low power dissipation to achieve good battery life and weight. The main feature of the research is to design a pseudodifferential transconductor circuit for a low supply voltage application with the targeted gain greater than 20 dB using Mentor Graphics software. The designs are done in Pyxis Schematic and Pyxis Layout using eldo platform for simulation to simulate the functionality of the transconductor circuit. From the postlayout simulation, with supply voltage of 1.2 V, the gain of 30 dB with cut-off frequency of 398 kHz has been achieved.

A low-power consumption internet-connected device has received considerable attention in recent years. Power amplifier (PA) is the most significant block in radio frequency (RF) transceivers because the PA consumes high power. Therefore, an efficient and low power consumption (PA) are necessary for wireless applications. This paper presents the design of 2.4 GHz two stage with cascode class E power amplifier for wireless application using CMOS 0.13-μm technology. The proposed design employed two stage topology with cascode class E configuration in order to achieve high efficiency. The simulation results show that the proposed PA delivers 35 % power added efficiency (PAE) and 22.6 dBm output power with 3.3 V power supply into a 50 Ω load.

This paper presents the design of an IoT based air pollution monitoring system to measure carbon dioxide gas, butane gas, humidity and temperature. The hardware consists of MQ-2 gas sensor, ESP8266 Wi-Fi module, DHT22 temperature and humidity sensors. Meanwhile, the software used in this prototype is the Arduino Integrated Development Environment (IDE) written in function C and C++. The monitoring system indicate air quality is below than 100 AQI for safety air quality and more than 200 AQI for hazardous air quality. The green LED illuminated indicates there is no hazardous gas detected. Meantime, when the butane gas or carbon dioxide gas is identified, the red LED is illuminated. All the data are sent through ThingSpeak and Blynk applications. In ThingSpeak and Blynk applications, the data are displayed and updated after detected by the sensors in every 15 seconds and 1 second. In the Blynk application, when the hazardous gas is detected, the Blynk application sends a notification to alert the users immediately.

A high dc voltage is commonly used in many process industries in testing, research laboratories and others. Currently, a high voltage dc is implemented using transformer. In this paper, a novel high voltage low current transformerless step-up dc-dc converter is presented. The proposed design consists of two step-up dc-dc converters with negative feedback signal and 15 stages of Cockcroft-Walton (C-W) voltage multiplier. The dc input voltage of 5 V triggers the first step-up dc-dc converter circuit to generate 30 V dc voltage and the second step-up dc-dc converter circuit boosts up to 100 V dc voltage. Further, diode-capacitor multiplier circuit is connected at the final stage to achieve 1.6 kV dc output voltages at 200 kHz switching frequency. The simulation results indicate that the proposed dc-dc converter can generate 1.548 kV dc voltage with a load current of 0.16 mA at 10 MΩ load resistor. Meanwhile, the experiment results show that the proposed dc-dc converter can generate 1.475 kV dc voltage with 80 % efficiency. The results validate both the simulation and experimental of the proposed high dc voltage power supply module.

This paper presents a study and analysis of high efficiency CMOS power amplifier (PA) for Internet of Thing (IoT) application. The studied mainly focused on the topology employed in designing high efficiency PA in gigahertz range frequencies. This study covers the basic class-E PA and the topologies in designing class-E PA such as single-stage, two-stage, multistage and differential. The circuits structure and the performances of class-E PA is discussed. The analysis is focusing on the efficiency of the proposed PA. The latest CMOS PAs developments have been studied and a summarization of the performance specification for different topologies are elaborated.

This paper presents a linear low-dropout (LDO) voltage regulator in 0.18-pm CMOS technology. The proposed LDO consists of voltage reference, error amplifier, pass device, output capacitor and resistive feedback network. A symmetrical operational transconductance amplifier (OTA) is implemented as an error amplifier and a PMOS transistor is used as a pass device to produce low dropout voltage and low quiescent current. The proposed design is simulated using Spectre simulator in Cadence software to verify its performances. The simulation results indicated that the LDO regulator achieves a regulated output voltage of 1.5 V with the ranges of supply voltage from 1.7 V to 2.0 V. The LDO regulator has a dropout voltage of 19.3 mV under maximum load current of 1.1 mA. The proposed LDO regulator is suitable for power management system.

In vehicular communication, signal transmission in vehicle-to-infrastructure (V2I) mode typically takes place on highways, urban, suburban and rural environments. The presence of buildings in these environments poses a challenge to model path loss (PL) due to multiple propagation mechanisms such as diffractions and reflections. However, very little attention has been made to address building effects on the performance of V2I communication links in microcell environment. This paper investigates signal propagation characteristics caused by the impact of building under micro-cellular environment whereby the base station or road-side-unit (RSU) is usually located under the rooftop of building to allow communication between RSU and mobile station or on-board-unit (OBU) on the road. The goal of this paper is to validate and discuss available path loss models based on effect of building obstruction towards RSU-OBU links specifically in residential housing area. The channel measurements are conducted based on static line-of-sight (LOS) settings of a real-world environment at 2.4 GHz frequency band using IEEE 802.15.4 XBee S2C compliant device to measure its receive power. The results are demonstrated based on received signal strength indicator (RSSI) and root mean square error (RMSE). The attenuation profile is validated and compared with suitable path loss models to evaluate best fit and most compatible model based on our measurements data and environment. The analysis shows that several V2I path loss models and V2V channel models are applicable to be used as a reference to model in LOS microcell environment with building obstruction. The finding shows that PL Urban yields the best fit V2I path loss model in terms of RMSE when compared to our measurement campaign at 2.4 GHz.

The amount of fertilisers affects electrical conductivity (EC), and it is one of the major causes of the paddy yield decrease. The overuse of fertilisers can lead to environmental pollution and contamination. This study designed to develop soil electrical conductivity (EC) sensing system in the paddy field using the smart farming application. In this work, the study conducted in Kampung Ladang, Kuala Perlis, and the soil samples collected from a random location at two different depths from the paddy field. The EC value for the developed system was near the calibration solutions (12880µS and 150000µS) and directly proportional to the temperature. From the laboratory soil results, the EC values of the soils were higher with fertiliser. However, the EC values for 0-10cm soil depth were higher than 10-20cm soil depth. The soil EC is inversely proportional to the depth of soil and directly proportional to the amount of nutrients. It observed that the soil EC is linearly related to the amount of nutrients and temperature. The EC value decreases with the increase of soil depth displays a low amount of salts in the deep soil, while, increases with the increase of temperature indicates high current flow.

A design of CMOS class-F power amplifier (PA) at 2.4-GHz for wireless transmitters is presented. The class-F PA design is implemented by using 0.13-μm CMOS process. The proposed class-F PA employs cascade topology. The transistor’s on resistance is decreased by designing the transistors in parallel. Therefore, the efficiency is increased. The first stage is a common-source driver stage is biased in a class-AB to provide sufficient input voltage swing for the amplifier stage, while the amplifier stage is biased in cut-off region. Therefore, the transistor can operate as a switching-mode for high efficiency. The simulation results show that the power added efficiency (PAE) of 60% is obtained at 1.3 V power supply and the PA delivers 12 dBm output power. The chip area is 0.66 mm2.

Hybrid Floating Point/Logarithmic Number System processor is an Arithmetic Logic Unit with hybrid architecture in which its data computation involves Floating Point (FLP) and Logarithmic Number System (LNS). LNS processor has high performance but requires complicated hardware to support its function, especially LNS addition and subtraction. Therefore, hybrid processor is proposed to perform multiplication/division in LNS, addition/subtraction in FLP. Through merging FLP and LNS, data computation can be done in a faster, precise and less complicated way. The proposed research is a 32-bit Hybrid FLP/LNS processor, which involving 32-bit fixed point data format and 32-bit single precision FLP format. The EDA tools used in developing and simulating this project is based on Synopsys Design Compiler and Altera Quartus II, and the Hardware Description Language used is Verilog HDL. Logical synthesis of this project is done by using Synopsys Design Compiler and its area, timing and power are validated.

In this paper, a variety of adder and multiplier are compared to be implemented in a new logarithmic number system (LNS). Both adder and multiplier are designed with a generic very high-speed integrated circuit hardware description language (Verilog) program. This makes it possible to achieve the optimum performance in latency and area of 0.18µm CMOS technologies LNS chip. Consequently, the optimal configurations vary with speed and area of the schemes and in some cases can be compact area, O(n), fast in latency O(log2 n) or optimized. The program was scripted based on fixed-point (FXP) adders and multipliers that yet will be implemented in LNS system. The functionality of the scheme was tested before synthesized. Outcomes show that Ladner Fisher (LF) adder and modified Baugh Wooley multiplier contribute to fast in latency and consume minimal area.

Advancement of the complexity digital design has inadvertently forces the pre-silicon verification to become an exceedingly important to find the bugs at infancy in an application of integrated chip design cycle. The complexity of the designs poses significance of the RTL validation to allow the bottleneck to be seen at the infancy in the design cycle and produces quality IC. As AMBA is one of the leading busing system used in high performance of SoC design that has been developed to become a family with different bus protocol such as ASB, APB, AHB, AXI and et al. Thus, this study shows the RTL validation platform of the fives digital IPs whose integrated together on the AMBA bus based on the APB and AHB protocol. The verification strategies of the module level is proposed in this paper and presents the strategies at the system level. Therefore, the result shows the percentage on the functionality of RTC covered by proposed techniques.

This paper presents a review on three types of techniques in designing digital all-pass filters based on group delay. All the three methods use the same basic concept rooting back to the requirement of a stable transfer function of the filter which should be a minimum-phase type, and the denominator group delay. The most optimized of the three is chosen to be implemented in MATLAB in order to decrease the group delay variation of a 5th order Chebyshev low-pass filter with cut-off frequency of 160 MHz. The digital transfer function of the low-pass filter is obtained from the analog transfer function by means of bilinear transformation. The sampling frequency of the digital LPF is 100 times the cut-off ffrequency to retain the response of the analog LPF. Both of the filters are then cascaded together and the overall group delays variations are analyzed. The variations of group delay shows a reduction but the price paid is the increase of the overall group delay of the system.

Computing alignment matrix score to search for regions of homology between biological sequences is time consuming task. This is due to the recursive nature of the dynamic programming-based algorithms such as the Smith-Waterman and the Needleman-Wunsch algorithmns. Typical FPGA-based protein sequencer comprises of two main logic blocks. One for computing alignment scores i.e. the processing element (PE), while another logic block for configuring the PE with coefficients. During alignment matrix computation, the logic block for configuring the PE are left unused until the time consuming alignment matrix computation finished. Therefore, a new technique, known as overlap computation and configuration (OCC) is proposed to minimize the time overhead for performing biological sequence alignment. The OCC technique simultaneously updating substitution matrix in a processing element (PE) systolic array, while computing alignment matrix scores. Results showed that, the sequencer achieves more than two order of magnitude speed-up higher compared to the state of the art, at negligible area overhead, if any.

This paper presents an ultra-wideband 3.1–4.9 GHz low noise amplifier (LNA) employing a sixth-order bandpass Chebyshev filter. The LNA has been designed using Silterra 0.18 μm CMOS technology at 1.8 V power supply. The simulation shows that the LNA attains a power gain of 14.1 dB with an input reflection coefficient less than −10 dB in frequency range of interest, a noise figure of 4.29 dB at 3.8 GHz, gain flatness of ±0.25 dB, a 1 dB compression point of −17.67 dBm, −6.90 dBm for IIP3 and power dissipation of 4.5 mW excluding the buffer stage.

Interdigitated electrodes (IDEs) are made of two individually addressable interdigitated comb-like electrode structures. IDEs are one of the most favored transducers, widely utilized in technological applications especially in the field of biological and chemical sensors due to their inexpensive, ease of fabrication process and high sensitivity. In order to detect and analyze a biochemical molecule or analyte, the impedance and capacitance signal need to be obtained. This paper investigates the working principle and influencer of the impedance and capacitance biosensors. The impedance biosensor depends on the resistance and capacitance while the capacitance biosensor influenced by the dielectric permittivity. However, the geometry and structures of the interdigitated electrodes affect both impedance and capacitance biosensor. The details have been discussed in this paper.

This paper presents the design of anti-theft/cable cut real time alert system using microcontroller and GSM technology. The detection part is using the electrical circuit wire connection in detecting the voltage drop of the cable inside the microcontroller digital input port. The GSM wireless modem is used to send the location of cable cut directly to the authority mobile phone. Microcontroller SK40C with Microchip PIC16F887 is used as a controller to control the wireless modem and also the detection device. The device is able to detect and display the location of the cable cut on the LCD display besides of and sending out the location of the cable break to the authority mobile phone wirelessly via SMS.

The development a high-performance design of analog circuits becomes increasingly challenging with the continuous trend towards reducing the voltage supply and low power consumption without neglecting the trade-off among other performance parameters. This paper presents the design and implementation of CMOS operational amplifier (op-amp) with integrated common-mode feedback (CMFB) circuit for data converter using 0.13-μm Silterra CMOS technology. The folded cascode topology is employed as a main op-amp design because it provides high gain and high bandwidth besides low power consumption. The simulation results indicate that the DC gain of 64.5 dB along 133.1 MHz unity gain bandwidth (UGB) is achieved for a 1 pF load capacitor. The slew rate of 22.6 V/μs, the phase margin (PM) of 68.4° with settling time of 72.4 ns are obtained. The power consumption of this op-amp is 0.3 mW through voltage supply of 1.8 V.

Bamboo charcoal was successfully carbonized at 500 °C and 800 °C using Malaysia buluh madu (Gigantochloa albociliata). Structural analysis was done using Atomic Force Microscopy (AFM) in two different solvents; ethanol and DI water. The functional groups of bamboo charcoal were confirmed using Fourier Transform Infrared Spectroscopy (FTIR). The adsorption property of bamboo charcoal solution was investigated at different concentrations of 0.2, 0.4 and 0.7 mg/mL, using methylene blue test and characterized using UV-Vis Spectroscopy. Based on the adsorption investigation, it shows that the adsorption was increased as the concentration increased. It was also shown that at higher temperature and longer duration time, the adsorption process is improved.

Vacuum filtration method was used in order to fabricate a homogeneous and uniform thin film of multi-layer graphene oxide on plastic substrate. This self-regulating technique allows the number of graphene oxide layer to be controlled thus controlling the film thickness by simply varying either the concentration of the graphene oxide in the suspension or the filtration volume. Measurement of the sheet resistance as a function of graphene oxide concentration in solution shows the percolation behavior of multi-layer films. The device was then exposed in nitrogen dioxide (NO2) environment at room temperature and 200 °C, under atmospheric pressure. Results demonstrate that the graphene oxide film shows good sensitivity and excellent recovery time using plastic substrate.

This paper describes the design of aquaponics water monitoring system using Arduino microcontroller. Arduino Development Environment (IDE) software is used to develop a program for the microcontroller to communicate with multiple sensors and other hardware. The circuit of pH sensor, temperature sensor, water sensor, servo, liquid crystal displays (LCD), peristaltic pump, solar and Global System for Mobile communication (GSM) are constructed and connected to the system. The system powered by a rechargeable battery using solar energy. When the results of pH, temperature and water sensor are out of range, a notification message will be sent to a mobile phone through GSM. If the pH of water is out of range, peristaltic pump is automatic on to maintain back the pH value of water. The water sensor is fixed in the siphon outlet water flow to detect water flow from grow bed to the fish tank. In addition, servo is used to auto feeding the fish for every 12 hours. Meanwhile, the LCD is indicated the pH, temperature, siphon outlet water flow and remaining time for the next feeding cycle. The pH and temperature of water are set in the ranges of 6 to 7 and 25 °C to 30 °C, respectively.

The efficient reduction of graphene oxide (rGO) was performed using Sodium Borohydride (NaBH4). These reduction approaches remove the majority of the oxygen-containing functional groups at the basal plane and surface of graphene oxide sheets. Structural and physiochemical properties of the GO were investigated with help of Atomic Force Microscopy (AFM), Transmission Electron Microscopy (TEM), Fourier Transform Infrared Spectroscopy (FTIR), and Ultraviolet-Visible-Near infrared (UV-Vis-NIR). The effects of the chemical reduction on a GO surface were analyzed using a Semiconductor Parameter Analyzer (SPA) in order to obtain the electrical resistance measurement. It was found that the resistance of reduced graphene oxide was greatly reduced when compared to the condition of before reduction process. Then, the formation of uniform thin film of rGO sheets was produced using vacuum filtration method in order to fabricate a gas sensor. In this project, plastic was used as a substrate. The sensor was then being e...

Carbon Nanotubes (CNTs) is known for their hydrophobicity ability. However, this ability can become the bottleneck for the application of CNTs where a highly dispersion of materials are needed. In this project, different dispersing agents were investigated namely dye molecules and chitosan. Three different dyes are studied with different concentration, including 0.05 % of chitosan. The dispersion quality is determined by examining through UV-Vis-NIR. The best dispersion quality investigated here is when the concentration of dye molecules is higher, which is around 2.5 mM.

This work proposed a low noise figure 2.4 GHz down-conversion CMOS mixer for wireless sensor network (WSN) application using 0.13-µm Silterra technology. The proposed down-conversion mixer converts a high radio frequency (RF) signal from 2.4 GHz to an intermediate frequency (IF) of 100 MHz through the use of a local oscillator signal (LO) of 2.3 GHz. The proposed mixer employs a double balance Gilbert-cell topology with integrated input matching at the input stage and a low pass filter at the IF stage. The simulation results indicate that the proposed mixer obtains lower noise figure (NF) of 5.21 dB with an input third-order intercept point (IIP3) of 0 dB. Furthermore, the conversion gain (CG) of 8.6 dB is achieved with the power consumption of 1.57 mW at 1.8 V supply voltage.

Connected car has become one of emerging technology in the automotive industries and vehicular communication studies on the other hand, has become one heavily researched topic in academia which focuses on the performance of various parameters upon vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) communication-based in the IEEE 802.11p vehicular communication studies. In urban environment, obstructions from existence of building, trees, street’s layout and other obstruction or objects can strongly influence the receive signal levels at 2.4 GHz frequency band. To ensure reliable and stable communication link for efficient future deployments of cooperative RSUs deployments, will require analyses on the signal strength upon environments that generally characterized by challenging propagation conditions. This article presents the results of experimental field testing of signal characteristics of different types of road topology such as grass, gravel and tar surface on open field environment. The results show that road topology or streets layout have an effect on V2I communication and the attenuation resulted from certain types of road’s surface can give significant impact on signal propagation.

A 28 GHz power amplifier (PA) using CMOS 0.18 μm Silterra process technology is reported. The cascade configuration has been adopted to obtain high Power Added Efficiency (PAE). To achieve low power consumption, the input stage adopts reverse body bias technique. The simulation results show that the proposed PA consumes 32.03mW and power gain (S21) of 9.51 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 11.10 dBm and maximum PAE of 16.55% with output 1-dB compression point (OP1dB) 8.44 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.

At present, the development of autonomous vehicle has altered the outlook of modern transportation worldwide. The state-of-the-art vehicular communication for transportation system is advancing, especially in vehicle to infrastructure (V2I) communication. An effective communication between vehicle and infrastructure has become a significant part of autonomous transportation criteria. The necessity for high quality of service communication inspire for good planning and preparation in communication process. Per se, this paper proposes vegetation attenuation models for advance planning of communication process between vehicle to infrastructure, defined mainly by plants, trees and vegetation along the roadways in Malaysia. The channel measurement performed in Universiti Malaysia Perlis test-bed having large tall trees and low shrubs along the routes resulted in several interesting results which would shape the planning of CAV communication. It is observed that communication close to low plantation or shrub requires high power consumption as the range is significantly reduced. It is also learned that certain types of plantations allows for different level of signal attenuation depending on the antenna heights. The research also found out that the attenuation profile follows strictly the log normal distribution and as such certain planning could be made to reshape the communication process to cater for this.

This paper presents a concurrent dual-band CMOS low noise amplifier (LNA) at operating frequency of 2.4 GHz and 5.2 GHz for WLAN applications. The proposed LNA employed cascode common source to obtain high gain using 0.13-µm CMOS technology. The concurrent dual-band frequencies are matched using LC network band-pass and band-stop notch filter at the input and output stages. The filters help to shape the frequency response of the proposed LNA. The simulation results indicate that the LNA achieves a forward gain of 21.8 dB and 14.22 dB, input return loss of -18 dB and -14 dB at 2.4 GHz and 5.2 GHz, respectively. The noise figure of 4.1 dB and 3.5 dB with the input third-order intercept points 7 dBm and 10 dBm are obtained at 2.4 GHz and 5.2 GHz, respectively. The LNA dissipates 2.4 mW power at 1.2 V supply voltage with a chip size of 1.69 mm2.

Rice is source of food calories and protein. This second most widely grown cereal crop is the staple food for more than half the world’s population especially in developing countries. The ability of global rice production to meet population demands (now estimated at more than 5 billion and projected to rise to 8.9 billion by 2050) remains in uncertainty in the near future unless challenges in rice production are properly addressed [1-3]. This paper proposed an IoT (Internet of things)-based paddy productivity monitoring and advisory system Using Dash7 Wireless Network Protocol. All collected data will be stored in a database management system to enable users to retrieve data either from tablets, smartphones or computers. The heart of the system is the ATmega328p microcontroller that will control the payload of the wireless network of dash7 and read data from sensor nodes. Results show all data from sensor nodes in representation of graph for analysis purpose.

In this paper, a Real Time Clock (RTC) system for a dedicated microcontroller is proposed to provide the customized microcontroller its own time and date system. The RTC is developed using Verilog Hardware Description Language (HDL) and simulated using Synopsys software. This RTC is developed with standard Advance Peripheral Bus (APB) to be interfacing with the microcontroller through Advanced Microcontroller Bus Architecture (AMBA). This RTC will be used as an on-chip RTC in the microcontroller system to provide precise time and date which can be used for various applications. The basic architecture of RTC, APB standard for interfacing the RTC with AMBA bus, and the result in term of RTL, waveform, and layout will be discussed in this documentation. For this research, the part covered is on the logic part of the RTC that is bus interface, register, frequency divider and counter.

This paper reviews of high efficiency CMOS power amplifiers (PAs) in millimeter (mm) wave Ka - Band applications. The study is focused on the challenges in designing PA especially in GHz frequencies inclusive of high gain, good input and output matching, efficiency, linearity, low group delay and low power consumption. Several works on CMOS PA from year 2009 to 2018 are discussed in this paper. Recent developments of CMOS PAs are examined and a comparison of the performance criteria of various techniques is presented.

A high linearity CMOS up-conversion mixer at 3.0–5.0 GHz for ultrawideband applications is presented. The proposed design is implemented in TSMC 0.18-μm CMOS technology. A Gilbert-cell active double-balanced mixer using a capacitor placed in parallel with the intrinsic gate-source capacitor of a core mixer to improve linearity is used. To further improve the linearity and input matching, source degeneration inductors is used. In addition, a current injection is designed to increase gain and obtain low power. A 100 MHz intermediate frequency input signal is converted to a 3.0–5.0 GHz radio frequency input signal. The measured input third-order intercept point (IIP3) is 13.5 dBm with a convention gain of 2.3 dB. Moreover, a low power of 7.1-mWwith a 1.2-V power supply is obtained. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:427–429, 2015

Enhanced feedback voltage of common mode feedback (CMFB) circuit is designed in this work for CMOS data sampling application using 0.18-μm Silterra process technology. The double error detecting point circuit is employed to associate with the feedback point in order to prevent the undesired voltage common mode at the output of operational transconductance amplifier (OTA). The PMOS input transistor for injecting the common mode voltage is used to fit in the limitation of voltage division in low power design. The feedback voltage is strongly pushed to have a stable value as to make the outputs of differential amplifier circuit swing at a nearly constant voltage at 1.2 V for enhancing accuracy of data converter.

Optical trapping of particles has become a powerful non-mechanical and non-destructive technique for precise particle positioning. The manipulation of particles in the evanescent field of a channel waveguide potentially allows for sorting and trapping of several particles and cells simultaneously. Channel waveguide designs can be further optimized to increase evanescent field prior to the fabrication process. This is crucial in order to make sure that the surface intensity is sufficient for optical trapping. Simulation configurations are explained in detail with specific simulation flow. Discussion on parameters optimization; physical geometry, optical polarization and wavelength is included in this paper. The effect of physical, optical parameters and beam spot size on evanescent field has been thoroughly discussed. These studies will continue toward the development of a novel copper ion-exchanged waveguide as a method of particle sorting, with biological cell propulsion studies presently underway.

Logarithmic number system can be highly considered as an alternative to floating-point, specifically for applications that require a wide dynamic range of numbers for their arithmetic operations. To date, its implementation is still restricted by complexity of performing addition and subtraction functions as a result of using large lookup tables. In this paper, a method is revealed to substantially reduce these tables by means of using second order co-transformation procedure. The results predominantly show that the proposed technique offers significantly better speed, area and accuracy than current state-of-the-art logarithmic number system.

The high voltage DC power supply widely used for space communication and for industry consist of multistage rectifier circuit. To produce 6KV output voltage, Cockroft-Walton multiplier circuits are applied by reducing number of stages from 1200 into 32 stages without using transformer. With the implementation of this technique, it can minimize the volume of the circuit to be integrated on a single chip and it also can reduce associated power loss in the circuit. By eliminating the transformer method, cost and size for making Cockroft-Walton Voltage Multiplier are reduced. Specification need to be considered for designing a multiplier is size of component must use within the range of expected load current and output voltage The details description of the simulation, design, development and implementation of this works are done using Cadence PSPICE software. Results are present in term of the performances and efficiency.

A homogeneous film of acid functionalized Carbon Nanotubes was deposited on the paper substrate using Langmuir-Blodgett technique. The palladium nanoparticles were dropped on the nanotubes network afterword for device enhancement. The sensitivity of the device towards hydrogen gas was tested at three temperatures; room temperature, 200 °C and 300 °C in atmospheric conditions. The results show that CNT network with Pd decorated has high sensing response up to 22 % recorded at room temperature.

Biological sequence alignment is time-consuming tasks. This is due to its repetitive alignment matrix scores calculations. The SSEARCH35 is the well-known ‘software-only’ sequence homology search tool. However, its sequential execution requires quadratic time complexity even when the software is executed in a sophisticated computer. Alternatively, sequence alignment is executed in hardware such as FPGA. FPGA allows for realization of systolic array (SA) architectures on its sea of logic gates. SA has been proven to address the aforementioned issues, whereby time required to compute alignment matrix scores in an n by n matrix significantly improved from n2 to 2n−1. However, SA requires more hardware resources as the processing element (PE) is replicated to increase performance throughput. This paper presents an optimized and parameterizable PE architecture targeting for DNA sequence alignment with both affine and linear gap penalty score. The PE was designed and synthesized in the Quartus II design environment. The DNA sequence alignment core was implemented on ALTERA Cyclone II FPGA with device number EP2C70F896C6. The functionality of PE has been successfully tested and verified against the SSEARCH35 software. Results have shown that, the core able to operate more than 50 MHz when implemented in FPGA. With less than 1% area utilization/PE, the FPGA device can generate more than 200 PEs for single pass processing.