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The paper presents an approach to solve the software and hardware related failures in edge-cloud environments, more precisely, in cloud manufacturing environments. The proposed approach, called TOLERANCER, is composed of distributed components that continuously interact in a peer to peer fashion. Such interaction aims to detect stress situations or node failures, and accordingly, TOLERANCER makes decisions to avoid or solve any potential system failures. The efficacy of the proposed approach is validated through a set of experiments, and the performance evaluation shows that it responds effectively to different faults scenarios.

The growing complexity of embedded and cyber-physical systems makes the design of all system components from scratch increasingly impractical. Consequently, already from early stages of a design flow, designers rely on prior experience, which comes in the form of legacy code or third-party intellectual property (IP) blocks. Current approaches partly address the co-simulation problem for specific scenarios in an ad hoc style. This work suggests a general method for co-simulation of heterogeneous IPs with a system modeling and simulation framework. The external IPs can be integrated as high-level models running in an external simulator or as software- and hardware-in-the-loop simulation with minimal effort. Examples of co-simulation scenarios for wrapping models with different semantics are presented together with their practical usage in two case studies. The presented method is also used to formulate a refinement-by-replacement workflow for IP-based system design., QC 20201217

The paper considers the issue of creating unified approaches to building test stands for software and hardware control systems. A universal architecture of the test bench is proposed and the author's method of constructing optimal test stands, obtained as a result of research in the field of complex automation of the test process, is described. The algorithm of directed search for the best test stand configuration is considered by example and the results of the implementation of the proposed method are demonstrated. © Published under licence by IOP Publishing Ltd.

We present the experimental evaluation of different security mechanisms applied to persistent state in intermittent computing. Whenever executions become intermittent because of energy scarcity, systems employ persistent state on non-volatile memories (NVMs) to ensure forward progress of applications. Persistent state spans operating system and network stack, as well as applications. While a device is off recharging energy buffers, persistent state on NVMs may be subject to security threats such as stealing sensitive information or tampering with configuration data, which may ultimately corrupt the device state and render the system unusable. Based on modern platforms of the Cortex M*series, we experimentally investigate the impact on typical intermittent computing workloads of different means to protect persistent state, including software and hardware implementations of staple encryption algorithms and the use of ARM TrustZone protection mechanisms. Our results indicate that i) software implementations bear a significant overhead in energy and time, sometimes harming forward progress, but also retaining the advantage of modularity and easier updates; ii) hardware implementations offer much lower overhead compared to their software counterparts, but require a deeper understanding of their internals to gauge their applicability in given application scenarios; and iii) TrustZone shows almost negligible overhead, yet it requires a different memory management and is only effective as long as attackers cannot directly access the NVMs., QC 20210907

Platforms are emerging that allow data scientists, software and hardware engineers to collaborate through organisational boundaries to develop systems of Artificial Intelligence (AI). Such collaboration involves the exchange of assets representing Intellectual Property (IP) of the collaborators. The tension between permitting access and protecting IP is thus one of the critical challenges faced by organisations willing to innovate through collaboration. Licensing is a common way to address the issue, but the influence of the licensing rules on the intended form of collaboration is still unclear.In this paper, we identify and analyse the rules that are used to regulate IP exchanges in two common forms of collaboration: a) competitions where one customer benchmarks and selects among multiple suppliers and b) consortium projects where multiple parties collaborate to product joint results. Due to our interest in AI, we have chosen to analyse the terms and conditions of competitions hosted on KaggleTM a leading online platform for Competitions. For consortium projects, we have analysed the DESCA Consortium Agreement template. DESCA is often used for European projects, an increasing number of which are used to fund AI innovation projects. We have applied In Vivo Coding and Concept Coding coding techniques to highlight rules applicable to IP exchange. We structured the findings in the form of tree graphs consisting of interdependent textual phrases to extract, group and compare the terms and conditions of IP sharing in each collaboration form and how they relate to the characteristics of the studied collaborations.The results indicate that each form of collaboration has its own set of rules that address comparable concerns but have different content. Practitioners, both platform providers and collaborators, can utilise our results to implement licensing for IP exchange that fits the desired type of collaboration. For researchers, our results represent a step towards the au

Commercial off-the-shelf (COTS)-centric cyber physical systems often contain software and hardware elements with life-spans shorter than the systems' intended life-span. Various studies have examined hardware obsolescence, although in most systems, software costs contribute as much, or more, to the total life cycle costs than hardware. The aim of our research effort is to explore, synthesize, and compile past research efforts on obsolescence in the context of COTS-based systems, and propose new ways to overcome related issues. This research effort suggests the need for systematic perspectives to streamline potentially overbearing acquisition processes while focusing on core critical aspects affecting systems sustainment and cost. Significant life cycle costs associated with obsolescence mitigation approaches, therefore, programmatic strategic planning should be adapted to include the context of obsolescence with the objective to improve the efficiency of new COTS-intensive CPS systems with enduring perspectives. The study reveals opportunities and challenges for obsolescence in COTS-based CPSs., QC 20200505

Virtual Reality (VR) applications put high demands on software and hardware in order to enable an immersive experience for the user and avoid causing simulator sickness. As soon as networks become part of the Motion-To-Photon (MTP) path between rendering and display, there is a risk for extraordinary delays that may impair Quality of Experience (QoE). This short paper provides an overview of latency measurements and models that are applicable to the MTP path, complemented by demands on user and network levels. It specifically reports on freeze duration measurements using a commercial TPCAST wireless VR solution, and identifies a corresponding stochastic model of the freeze length distribution, which may serve as disturbance model for VR QoE studies. © 2019 IEEE.

Formal verification of systems-level software such as hypervisors and operating systems can enhance system trustworthiness. However, without taking low level features like caches into account the verification may become unsound. While this is a well-known fact w.r.t. timing leaks, few works have addressed latent cache storage side-channels, whose effects are not limited to information leakage. We present a verification methodology to analyse soundness of countermeasures used to neutralise these channels. We apply the proposed methodology to existing countermeasures, showing that they allow to restore integrity of the system. We decompose the proof effort into verification conditions that allow for an easy adaption of our strategy to various software and hardware platforms. As case study, we extend the verification of an existing hypervisor whose integrity can be tampered using cache storage channels. We used the HOL4 theorem prover to validate our security analysis, applying the verification methodology to a generic hardware model., QC 20180516QC 20181012, trustfull, cerces

Mission-critical Internet of Things (MC-IoT) systems involve heterogeneous things from both the digital and physical worlds. They run applications whose failure might cause significant and possibly dramatic consequences, such as interruption of public services, significant business losses, and deterioration of enterprise operations. These applications require not only high availability, reliability, safety, and security but also regulatory compliance, scalability, and serviceability. At the same time, they're exposed to various facets of uncertainty, spanning from software and hardware variability to mission planning and execution in possibly unforeseeable environments. Model-driven engineering can potentially meet these challenges and better enable the adoption of MC-IoT systems.

A theory of quantum models, methods and algorithms for improving the performance of existing software and hardware tools for analysis and synthesis of digital computing devices by increasing the dimension of the data structures and memory are proposed. The basic concepts, terminology and definitions are introduced, which are necessary for the understanding the theory and practice of quantum computation.

This paper describes a system for accommodating active listening for persons with hearing aids or cochlear implants, with a special focus on children with complex needs, for instance at an early stage of cognitive development and with additional physical disabilities. The system is called Ljudskrapan (or the Soundscraper in English) and consists of a software part in Pure data and a hardware part using an Arduino microcontroller with a combination of sensors. For both the software and hardware development, one of the most important aspects was to always ensure that the system was flexible enough to cater for the very different conditions that are characteristic of the intended user group.The Soundscraper has been tested with 25 children with good results. An increased attention span was reported, as well as surprising and positive reactions from children where the caregivers were unsure whether they could hear at all. The sound generating models, the sensors and the parameter mapping were simple, but provided a controllable and complex enough sound environment even with limited interaction., QC 20120111. QC 20160115, Ljudskrapan

Verification of today's Systems-on-Chip (SoC) occur at low abstraction-levels, typically at register-transfer level (RTL). As the complexity of SoC designs grows, it is increasingly important to move verification to higher abstraction levels. Hardware/software co-simulation is a step in this direction, but is not sufficient due to inaccurate processor models, and slow hardware simulation speeds. System level monitoring, commonly used for event-based software debugging, provides information about task scheduling events, inter-task communication and synchronisation, semaphores/resources, I/O interrupts, etc. We present MAMon, a monitoring system that can both monitor the logic-level and the system-level in single/multiprocessor SoCs. A small hardware probe-unit is integrated in the SoC design and connects via a parallel port link to a host-based monitoring tool environment. The probe-unit collects all events in the target system in runtime, and timestamps them with a resolution of J ps. The events are then stored in a database on the host for further processing. The paper will describe MAMon and how it works for software and hardware monitoring. The paper also describe how system-level monitoring can be achieved non-instrusively by using a hardware-based Real-Time Kernel.