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Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

To get stable perpendicularly magnetized tunnel junctions at small device dimensions, composite free layers that comprise two MgO/FeCoB interfaces as sources of interface anisotropy are generally used. Proper cristallisation and annealing robustness is typically ensured by the insertion of a spacer layer of the early transition metal series within the FeCoB layer. We study the influence of the spacer thickness and growth condition on the switching metrics of tunnel junctions thermally annealed at 400$^\circ$C for the case of 1-4 \r{A} Ta spacers. Thick Ta spacer results in a large anisotropies indicative of a better defined top FeCoB/MgO interface, but this is achieved at the systematic expense of a stronger damping. For the best anisotropy-damping compromise, junctions of diameter 22 nm can still be stable and spin-torque switched. Coercivity and inhomogeneous linewidth broadening, likely arising from roughness at the FeCoB/Ta interface, can be reduced if a sacrificial Mg layer is inserted before the Ta spacer deposition., Comment: To appear in IEEE magnetics letters

The hybrid free layer (HFL) design consisting of a single layer of CoFeB coupled via a spacer to [Co/Ni] multilayers was proposed previously to increase perpendicular magnetic anisotropy in the free layer of top-pinned magnetic tunnel junction stacks. It is thus expected that a high thermal stability factor ( $\Delta$ ) can be achieved in devices with small dimensions, which is required for data retention in high-density memory applications. Here, we report on the electrical and magnetic properties of the HFL in devices with various critical dimensions (CD), in which case the [Co/Ni] multilayers in the HFL have only one Co/Ni bilayer on Pt seed. It is shown first that the HFL can provide larger coercive field ( $H_{c}$ ) than dual-MgO FL counterparts. $\mu _{0}H_{c}$ around 125 mT is achieved in sub-20 nm devices with the HFL. To derive $\Delta$ , the field sweep method was applied. The fitting of the switching probability versus applied field was compared for a macrospin reversal and a domain wall mediated reversal (DWMR). The DWMR model is valid when the CD is larger than around 40 nm in both dual-MgO FL and HFL cases, where the switching is realized through domain wall motion as shown via micromagnetic simulations. In both regimes, the HFL provides a higher $\Delta$ than the dual-MgO FL.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm 2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

For the first time at our knowledge, we demonstrate a sub-µm indium-gallium-zinc oxide (a-IGZO) (vertical) Schottky diodes on a 300mm platform. We demonstrate that the choice of a suitable Al2O3-based encapsulation layer is critical in order to achieve near-ideal diode parameters (n, φSBH) and uniform wafer-level behavior. We show, for the smallest devices of 0.5µm x 0.5µm, an ideality factor n of 1.5 and Schottky barrier height (φSBH) of 0.7 eV while simultaneously achieving a peak current density of 0.1 MA/cm2.

Top-pinned perpendicular magnetic tunnel junctions featuring a synthetic antiferromagnet (SAF) have been extensively studied for spin-transfer-torque magnetic random-access memory (STT-MRAM). However, degraded device performance after annealing remains a problem for this design, and hinders integration with CMOS technology. This study instead uses a synthetic $f\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}r\phantom{\rule{0}{0ex}}r\phantom{\rule{0}{0ex}}o\phantom{\rule{0}{0ex}}m\phantom{\rule{0}{0ex}}a\phantom{\rule{0}{0ex}}g\phantom{\rule{0}{0ex}}n\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}t\phantom{\rule{0}{0ex}}i\phantom{\rule{0}{0ex}}c$ (SFM) pinning layer to enable high thermal tolerance in STT-MRAM stacks. Experiment and simulation confirm functionality in 20-nm devices, including current switching. The proposed design contributes significantly to the scalability of STT-MRAM, and enables future applications requiring a top-pinned stack.

The CoFeB/MgO/CoFeB magnetic tunnel junction (MTJ) is the central element of any high performance perpendicular Magnetoresistive Random Access Memory (MRAM) device. The MgO tunnel barrier, in contact with CoFeB films at both sides in the magnetic tunnel junction, provides a high tunnel magneto resistance (TMR) and perpendicular magnetic anisotropy (PMA) thanks to the high crystalline quality of the MgO/CoFeB interface achieved upon post-deposition annealing. We study MgGa2O4 as an alternative barrier material due to its lower bandgap and show how to introduce it into state-of-the-art perpendicular MRAM stacks. We demonstrate that thin MgO films at both sides of the barrier are key to ensure a proper crystallization and induce reference layer and free layer perpendicular magnetic anisotropy. Consequently, a stack incorporating a MgGaxOy barrier with full PMA and TMR > 100% can be fabricated with a resistance-area (RA) product as low as 50 Ω μm2, which is of strong interest as a potential barrier in the field of voltage control magnetic anisotropy MRAM.

Spin-transfer torque magnetic random access memory (STT-MRAM) is currently explored to challenge the dynamic random access memory and embedded memory applications. Perpendicular magnetic tunnel junction (p-MTJ) stacks used in the STT-MRAM must be compatible with CMOS back-end-of-line processing, such as high perpendicular magnetic anisotropy, high tunnel magnetoresistance (TMR), and intact resistance area (RA) product at temperatures, as high as 400 °C. In this paper, we deposited a bottom-pinned Co/Ni-based p-MTJ stack with a trilayered Co/spacer/CoFeB as a reference layer and a CoFeB film as the storage layer. By replacing the standard Ta spacer material with CoFeBTa, the thickness of the spacer layer can be increased from 4 to 8 A without TMR and RA penalty, which is beneficial to process controllability. Moreover, the TMR increases for an 8 A CoFeB polarizer from 125% to 145% for a similar RA product after a 300 °C 30 min anneal. In addition, the thermal budget of the p-MTJ stack containing a CoFeBTa spacer was improved. The p-MTJ stack with a 12 A CoFeBTa reference layer spacer can even withstand annealing at 400 °C for 90 min and can retain a TMR value of 100% at RA 10 $\Omega \cdot \mu \text{m}^{2}$ , while TMR dropped below 40% for the p-MTJ stack containing a pure Ta spacer layer.

Magnetic random-access memory (MRAM) stacks with perpendicular magnetic anisotropy (PMA) based on spin-transfer torque (STT) are expected to be used in the next generation of high speed, low power, memory applications. As device dimensions are scaled down, the total PMA of the MgO/CoFeB system is increased by embedding CoFeB between two MgO layers. We compare the properties of a continuous free layer versus a composite design in which a Ta insertion layer is introduced into the free layer, the latter being the design of choice in the literature. We used transmission electron microscopy and secondary ion mass spectrometry depth profiling to determine the role the Ta spacer plays as an oxygen scavenger. Our results indicate that optimal control of the oxygen content and diffusion are important for the thermal robustness and PMA of the free layers embedded between two MgO layers.

We investigate the Gilbert damping and the magnetization switching of perpendicularly magnetized FeCoB-based free layers embedded in tunnel junctions adequate for spin-torque operated memories. We study the influence of the boron content in MgO / FeCoB /Ta systems alloys on their Gilbert damping after crystallization annealing. Increasing the boron content from 20 to 30\% increases the crystallization temperature, thereby postponing the onset of elemental diffusion within the free layer. This reduction of the interdiffusion of the Ta atoms helps maintaining the Gilbert damping at a low level of 0.009 without any penalty on the anisotropy and the magneto-transport properties up to the 400$^\circ$C annealing required in CMOS back-end of line processing. In addition, we show that dual MgO free layers of composition MgO/FeCoB/Ta/FeCoB/MgO have a substantially lower damping than their MgO/FeCoB/Ta counterparts, reaching damping parameters as low as 0.0039 for a 3 \r{A} thick Tantalum spacer. This confirms that the dominant channel of damping is the presence of Ta impurities within the FeCoB alloy. On optimized tunnel junctions, we then study the duration of the switching events induced by spin-transfer-torque. We focus on the sub-threshold thermally activated switching in optimal applied field conditions. From the electrical signatures of the switching, we infer that once the nucleation has occurred, the reversal proceeds by a domain wall sweeping though the device at a few 10 m/s. The smaller the device, the faster its switching. We present an analytical model to account for our findings. The domain wall velocity is predicted to scale linearly with the current for devices much larger than the wall width. The wall velocity depends on the Bloch domain wall width, such that the devices with the lowest exchange stiffness will be the ones that host the domain walls with the slowest mobilities., Comment: Submitted to the proceedings of TMRC 2017

For the first time, we report on 400°C compatible top-pinned perpendicular magnetic tunnel junction (MTJ) stacks with dual MgO free layer for STT-MRAM applications. Using a texture-inducing parallel-coupling barrier layer (TICPB), we enforce the pinning layer and control diffusion, which enables BEOL compatibility while keeping TMR as high as 184%. In addition, we demonstrate that using such synthetic ferro-magnetic stack (SFM) design with TICPB layer allows a free layer off-set control and a switching current of 3.8 MA/cm2 in 25 nm e-CD devices.

The effect of four different seed layers-Ru, Hf/Ru, Ru/Hf, and Hf on the magnetic properties of [Co 5/Pt 3 A] multilayer (ML) stack with perpendicular magnetic anisotropy was investigated. The structural quality of the ML stacks was studied and correlated with the magnetic properties. Among the abovementioned seed layers, Ru promotes stronger fcc (111) texture in the ML due to less lattice mismatch (8% between Ru and Co) in Co/Pt MLs. As a result, higher anisotropy field (H K ~ 17 kOe) and larger effective perpendicular anisotropy (K eff ~ 1.2 × 10 7 erg/cm 3 ) were achieved for the MLs on Ru seed layer compared with other seed layers after annealing at 300 °C for 30 min. The perpendicular magnetic anisotropy of the MLs is improved at higher annealing temperature up to 400 °C for Ru and Hf/Ru seed layer. For the Co/Pt MLs on Ru, 1.3 × 10 7 erg/cm 3 perpendicular magnetic anisotropy was obtained even after annealing at 400 °C. Detail investigations of postannealing stability of the ML films on different seed layers were also discussed. The magnetic properties and structural properties of the films on four different seed layers were characterized after rapid thermal annealing process at 300 °C, 350 °C, and 400 °C for 30 min annealing duration. The high temperature endurance limit up to 400 °C for 30 min of the Co/Pt MLs on Ru and Hf/Ru seed layers makes them compatible with the back-end-of-line process temperature.

To ensure data retention in high-density spin-transfer-torque magnetic random access memory (STT-MRAM), a [Co/Ni]-CoFeB hybrid free layer (HFL) with a high energy barrier was proposed for small-dimension magnetic tunnel junctions. Its behavior on device level, however, needs further research. In particular, the impact of the interlayer that provides magnetic coupling between the [Co/Ni] multilayers and the CoFeB on the spin-torque switching is not known. In this paper, both macrospin modeling and micromagnetic simulations are used to study the influence of interlayer exchange coupling (IEC) on the switching behavior of the HFL for different device sizes. Both methods provide the optimal value for the coupling constant ( $J_{{\mathrm{ ex}},o}$ ) and switching current ( $J_{{\mathrm{ sw}},o}$ ), as well as their size dependence, to realize HFL switching with the lowest energy consumption. In addition to the simulations, control of the IEC in the HFL by introducing a TaCoFeB interlayer and a Co termination layer on the [Co/Ni] part is shown, and a broad $J_{{\mathrm{ ex}},o}$ range is achieved without compromising the magnetotransport properties of the stacks. Both simulations and experimental work show that the HFL design with adequate interlayer engineering can be a viable route for high-density STT-MRAM devices and other spintronic applications.

Perpendicular magnetic tunnel junctions (MTJ) are widely being researched as they are the key component in advanced spin transfer torque magnetic random access memory (STT-MRAM).

The nanometer thin MgO barrier and the large write currents for STT-MRAM, result in an endurance bottle neck due to oxide breakdown. In this paper we present an in-depth analysis of the impact of processing on barrier breakdown, including etch techniques (ion beam etch and reactive ion etch), post etch treatments and variations of the spacer layers in the MRAM stack. We find that variability in breakdown characteristics can be significantly reduced using an optimized etch. Secondly we propose an oxygen scavenging model to explain the different reliability behavior for various stack configurations.

[Co/Ni] multilayers with perpendicular magnetic anisotropy (PMA) have been researched and applied in various spintronic applications. Typically the seed layer material is studied to provide the desired face-centered cubic (\textit{fcc}) texture to the [Co/Ni] to obtain PMA. The integration of [Co/Ni] in back-end-of-line (BEOL) processes also requires the PMA to survive post-annealing. In this paper, the impact of NiCr, Pt, Ru, and Ta seed layers on the structural and magnetic properties of [Co(0.3 nm)/Ni(0.6 nm)] multilayers is investigated before and after annealing. The multilayers were deposited \textit{in-situ} on different seeds via physical vapor deposition at room temperature. The as-deposited [Co/Ni] films show the required \textit{fcc}(111) texture on all seeds, but PMA is only observed on Pt and Ru. In-plane magnetic anisotropy (IMA) is obtained on NiCr and Ta seeds, which is attributed to strain-induced PMA loss. PMA is maintained on all seeds after post-annealing up to 400$^{\circ}$C. The largest effective perpendicular anisotropy energy ($K_U^{\mathrm{eff}}\approx 2\times10^5$J/m$^3$) after annealing is achieved on NiCr seed. The evolution of PMA upon annealing cannot be explained by further crystallization during annealing or strain-induced PMA, nor can the observed magnetization loss and the increased damping after annealing. Here we identify the diffusion of the non-magnetic materials from the seed into [Co/Ni] as the major driver of the changes in the magnetic properties. By selecting the seed and post-annealing temperature, the [Co/Ni] can be tuned in a broad range for both PMA and damping., Comment: 9 pages, 11 figures

We study the annealing stability of bottom-pinned perpendicularly magnetized magnetic tunnel junctions based on dual MgO free layers and thin fixed systems comprising a hard [Co/Ni] multilayer antiferromagnetically coupled to thin a Co reference layer and a FeCoB polarizing layer. Using conventional magnetometry and advanced broadband ferromagnetic resonance, we identify the properties of each sub-unit of the magnetic tunnel junction and demonstrate that this material option can ensure a satisfactory resilience to the 400$^\circ$C thermal annealing needed in solid-state magnetic memory applications. The dual MgO free layer possesses an anneal-robust 0.4 T effective anisotropy and suffers only a minor increase of its Gilbert damping from 0.007 to 0.010 for the toughest annealing conditions. Within the fixed system, the ferro-coupler and texture-breaking TaFeCoB layer keeps an interlayer exchange above 0.8 mJ/m$^2$, while the Ru antiferrocoupler layer within the synthetic antiferromagnet maintains a coupling above -0.5 mJ/m$^2$. These two strong couplings maintain the overall functionality of the tunnel junction upon the toughest annealing despite the gradual degradation of the thin Co layer anisotropy that may reduce the operation margin in spin torque memory applications. Based on these findings, we propose further optimization routes for the next generation magnetic tunnel junctions.

Strained Ge channel PFETs have the potential to outperform state-of-the-art strained Si channel PFETs. This paper describes the integration aspects for strained Ge channel devices based on TCAD simulations and experimental observations. The most scalable way of introducing channel stress is by the use of Si 1− x Ge x strain relaxed buffers (SRB) and/or high Ge-content source/drain stressors, selectively grown in STI. Reduction of the thermal budget, damage and Ge loss during subsequent processing are key to maintain the high strain in the Ge channel till the end of processing.

We proposed a new, simpler, and fully BEOL CMOS-compatible TiN/HfO2/TiN RRAM stack using the Plasma Enhanced Atomic Layer Deposition (PEALD) for the top-electrode TiN processing, demonstrating attractive bipolar switching properties (by positive RESET voltage to the PEALD TiN) in a functional size down to 2275nm2 (35nmi?65nm). Stable switching was observed between a High-Resistive State HRS (~1M?) and a Low-Resistive State LRS (~100k?), using a low program current of ~1µA. Two different LRS states can be obtained depending on the current compliance (CC) during SET switching, either 100µA (high-CC LRS) or 10µA (low-CC LRS), resulting, respectively in LRS resistances of 10k? or 100k?. The projected retention stability of low-CC LRS is ?10years at 80?C, which is the retention minimum of the TiN/HfO2/TiN RRAM stack. The temperature-dependent resistance showed a non-metallic behavior for the low-CC LRS state (~100k?), suggesting gentle filament formation.

We report on the electrical and physical properties of Cu2ZnSnSe4 (CZTSe) solar cells consisting of an absorber layer fabricated by selenization of sputtered Cu, Zn, Sn multilayers. Cross-section scanning electron microscopy images show that the polycrystalline absorber layers are approximately 1 μm thick and that the typical grain size is of the order of 1 μm. Energy-dispersive X-ray spectroscopy measurements show Cu-poor and Zn-rich compositions with Cu/(Zn + Sn) ~ 0.8 and Zn/Sn ~ 1.2. Solar cells are fabricated out of this absorber material using a standard process flow for chalcogenide solar cells. Under AM1.5 G illumination, the best 1 × 1 cm2 CZTSe solar cell shows an efficiency of 6.3% with a maximum short circuit current of 31.3 mA/cm2, an open circuit voltage of 0.39 V and a fill factor of 52%. Doping density of the absorber layers is derived using the drivel level capacitance profiling (DLCP) technique, showing low p-type doping density which seems to increase exponentially with the Zn/Sn ratio. Comparing the values obtained from DLCP to the ones derived from Mott–Schottky plots of the same devices, it is shown that for CZTSe care has to be taken when deriving the doping density. Similar to copper indium gallium selenide junctions, Mott–Schottky plots overestimate the amount of free carriers in the buffer due to the presence of fast defect states inside the bandgap.

STT-MRAM is a promising non-volatile memory. For reliable lifetime predictions, a correct voltage acceleration model is essential. However, there is no consensus over what acceleration model to use. In this paper we study barrier breakdown time over an extended time range. With a maximum likelihood ratio method, we test the statistical significance of fits for different voltage acceleration models. We find that the power law best describes voltage acceleration. In addition we observe that the breakdown time is independent of duty cycle or pulse width.

A new carbon-based thermal stability improvement technique is proposed for nickel silicide. Carbon implantation is well known to improve the thermal stability of Ni-based silicides, but its process window is small. An experiment has been performed to identify and introduce new process steps which improve the thermal stability and which can be integrated into a CMOS technology platform without a significant cost increase. No yield issues have been observed up to 700^oC 30min post-silicidation thermal budget even for the narrowest silicided silicon lines. NiPtSi encroachment, which is one of the main yield killers for Sub-65nm technologies, has not been seen. The device scalability is not affected and a similar performance has been achieved with an additional post-silicidation thermal budget. Through in-depth understanding of this approach, new integration schemes like for instance a gate-last process flow can be envisioned.

Carbon nanotubes (CNTs) are considered a promising material for interconnects in the future generations of microchips because of their low electrical resistance and excellent mechanical stability. In particular, CNT-based contacts appear advantageous when compared with current tungsten or copper technologies and could therefore find an application as metal contacts interconnecting the transistors with the back end of line of the microchip. In this work, the integration of vertical CNT bundles in sub-micron contact holes is evaluated at wafer scale and the major integration challenges encountered in the practical realization of the process are discussed. Nickel PVD films were used to selectively grow CNT into the contact holes at temperatures as low as 400^oC, which is the thermal budget available for contacts. The height of the contacts and the length of the CNT are controlled by a chemical mechanical polishing step (CMP) after embedding the CNT into SiO"2. Ti/Au metal pads are then formed onto the CNT bundles by PVD and lift-off. The integrated CNT are electrically characterized and an annealing treatment was found to improve the CNT-via resistance. As the electrical properties of the CNT can be evaluated, the structure and the process presented constitute a test vehicle for the development of high-quality CNT-contacts.

In the framework of Resistive RAM we are investigating if the metal to insulator transition in vanadium dioxide can be used for memory applications. We investigate vanadium dioxide production by low pressure oxidation of metallic vanadium and demonstrate samples with 4 orders of magnitude transition in resistivity. We show that the relaxation times to the coexistence state are compatible with non-volatile memory requirements being longer than 10 years. We also investigate how metal doping influences the transition temperature.

An overview of silicides and germanides for nano-CMOS applications is presented. The historical evolution describing the migration from the use of Ti silicide to Co silicide to Ni silicide as contacting material is first discussed. These changes in silicide material were mainly motivated by the inability to form the target low resistivity silicide phase in small structures due to low nucleation density. This issue was found first for the low resistivity C54 TiSi 2 at linewidths below 200 nm and later for the low resistivity CoSi 2 , at linewidths below 40 nm. A detailed description of scalability and thermal stability issues for NiSi is then presented. No nucleation issues were found in small structures for NiSi, which grows by diffusion or interface limited kinetics with Ni as main moving species. However, silicidation can be excessive in small structures due to Ni diffusion from surrounding areas, resulting in thicker films than targeted in small devices. This can be controlled by using a silicidation process with two rapid thermal processing steps, the first one to control the amount of Ni reacted and the second one to convert the silicide to the target low resistivity monosilicide phase. One of the main issues for applications of NiSi is its low thermal stability: thin NiSi films agglomerate at relatively low temperatures. The process window and thermal stability of Ni and Pt-based films reacted with Si, Si:Ge and Si:C substrates is reviewed. Addition of Ge is shown to degrade thermal stability while addition of C or Pt improves it. Contact resistivity considerations and implementation of dual band-edge silicides are discussed, as well as promising results for the extension of Ni-based silicides to future nodes. Finally a brief overview of germanides is presented discussing NiGe and PdGe as main candidates.

The thermal stability of Ni(Pt)-silicides by carbon implantation was evaluated. The Ni(Pt)-silicide morphology and phase formation were studied by means of sheet resistance (Rs) measurements, scanning electron microscopy (SEM) and transmission electron microscopy (TEM) inspection, energy dispersive spectroscopy (EDS) and X-ray diffraction (XRD) analysis. The substrate crystallinity, carbon implantation dose and energy and the anneal conditions determine the stability of the silicide. Platinum and carbon increase the phase stability of Ni-silicide at high temperatures by increasing the disilicide nucleation temperature. The dominant degradation mechanism is morphological degradation for the NiPtSi:C films whereas transition to the NiSi2 phase is the dominant degradation mechanism for NiSi:C films. As compared to carbon incorporation by epitaxial growth of Si:C, the carbon implant has the advantage of being a simple technique that can also be applied to pMOS devices.

Low Vt Ni fully silicided (FUSI) devices are demonstrated making use of Al implantation for pMOS and Yb or Yb+P implantation for nMOS combined with Ni-silicide phase engineering. When Yb(+P) and Al implantation are followed by a high temperature anneal, significant segregation of Yb or Al toward the Ni-FUSI/SiON interface is observed and large Vt shifts of 450 mV (330 mV) and 200 mV are obtained for nMOS NiSi FUSI/SiON devices and pMOS Ni-rich FUSI/SiON devices, respectively, as compared to the undoped reference devices. The Vt shifts are preserved down to the shortest gate lengths. For both Al and Yb, the Vt shifts are explained by the dopants reacting with and modifying the dielectric. Thus, the low Vt dual implantation approach proposed achieves a low-cost "dual dielectric" implementation without the need of dual deposition of dielectrics or capping layers. In the case of Yb implantation followed by a high temperature anneal, a significant reduction in the inversion dielectric thickness is observed, indicating that the reaction between Yb and SiON results in the formation of a high-k dielectric. The Yb diffusion and reaction at the interface can be engineered using a P coimplant.

Ni(alloy) silicides have recently gained much attention due to their improved properties. Ni(Pt)Si has indeed become one of most promising candidates to replace NiSi as contact electrodes. To avoid bridging at the spacers and the isolation areas, after self-aligned silicidation (salicidation), un-reacted NiPt needs to be removed. This post salicidation clean process has to be selective towards all possibly exposed materials such as Si3N4 (spacers), SiO2 (field oxide), NiPtSi (contact and gate electrodes), and NiPtSiGe (contact electrodes of source/drain for strain applications). In this work, it is found that dilute HCl/HNO3 mixtures can well be used for NiPt post salicidation clean. It is shown that this process has a high etch rate for NiPt and a high selectivity towards other possibly exposed materials. Furthermore, the sheet resistance and the thickness of the silicides after this selective etch are well within specification providing a clean, environmentally-friendly process with low cost-of-ownership.

The study of reliability and understanding of the MgO barrier breakdown mechanism is essential for the development of STT-MRAM, a promising non-volatile memory. However, for STT-MRAM it is unclear what the preferred method is for studying barrier breakdown. In this paper we compare four point probe Ramped Voltage Stress (4PP-RVS) with a conventional Constant Voltage Stress (CVS) technique and with pulsed breakdown (RF-BD). We show the equivalence of breakdown time distributions determined by 4PP-RVS and CVS. 4PP makes the investigation of area scaling possible and avoids potential lifetime misjudgments of more than one order of magnitude. In a short and predictable time RVS can measure large populations subject to strong lifetime variability, typical for STT-MRAM cells. We also compare 4PP-RVS with pulsed breakdown (RF-BD) and observe a more favorable reliability for RF-BD. 4PP-RVS allows an efficient in depth breakdown analysis for STT-MRAM.

NiPt (10% Pt) and Pt were investigated as alternatives to Ni for contact formation to SiGe source/drain. The germanosilicide phase formation and morphology were studied by means of sheet resistance measurements, XRD (X-ray diffraction) analysis and SEM (scanning electron microscopy) inspection. From isochronal and isothermal anneals it is found that NiPt- and Pt-germanosilicide have better thermal stability compared to Ni-germanosilicide. NiPt-germanosilicide degrades morphologically, while still in the monogermanosilicide phase.

Integration of recessed Si:C source/drain (S/D) for deep sub- micron nMOSFET devices results in substantial improvement of electron mobility and drive current due to introduction of tensile strain in the channel. The compatibility of Ni-silicide contacts with Si:C source/drain is investigated in this paper. The Ni-silicide morphology and phase formation were studied by means of sheet resistance measurements, X-Ray Diffraction (XRD) and Energy Dispersive Spectroscopy (EDS) analysis, Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM) inspection. The carbon concentration and profile in the NiSi:C film was studied by Secondary Ion Mass Spectrometry (SIMS) analysis. The strain in the Si:C substrate and NiSi:C film was studied by high resolution XRD (HRXRD). This paper demonstrates that Ni-silicide is compatible with Si:C. The tensile strain in Si:C is maintained after Ni-silicidation. The addition of carbon to silicon is found to stabilize the silicide morphology.

Excellent tunnel magneto resistance (TMR) values of 143% at resistance-area products (RA) of 4.7 Ωµm2 from 11nm thin Co/Ni based perpendicular magnetic tunnel junctions (p-MTJ) was achieved. Engineered wetting layer (WL), seed layer (SL) and the introduction of newly designed inner synthetic anti-ferromagnetic (iSAF) pinned layer in combination with ultra-smooth bottom electrode (roughness 0.5 A) was yielded to vertically scaled 11nm thick Co/Ni p-MTJ stack with excellent magnetic properties. The introduction of iSAF layer demonstrates for the 1st time the free layer offset field controllability (< 100 Oe) of the spin-transfer-torque (STT) magnetic random access memory (MRAM) device down to 12 nm in diameter.

Arctic ecosystems are known to be extremely vulnerable to climate change. As the Intergovernmental Panel on Climate Change scenarios project extreme climate events to increase in frequency and severity, we exposed High Arctic tundra plots during 8 days in summer to a temperature rise of approximately 9°C, induced by infrared irradiation, followed by a recovery period. Increased plant growth rates during the heat wave, increased green cover at the end of the heat wave and higher chlorophyll concentrations of all four predominating species (Salix arctica Pall., Arctagrostis latifolia Griseb., Carex bigelowii Torr. ex Schwein and Polygonum viviparum L.) after the recovery period, indicated stimulation of vegetative growth. Improved plant performance during the heat wave was confirmed at plant level by higher leaf photochemical efficiency (F

Tundra ecosystems constitute large stocks of carbon and might therefore, if climate warming releases CO2, induce positive feedback and amplify temperature increase. We studied the effect of a 2.5°C temperature increment, induced by controlled infrared irradiation, on various components of the carbon balance of a High Arctic tundra ecosystem at Zackenberg in Northeast Greenland (74°N, 21°W) over the 1999 growing season. Gross photosynthesis (Pgross), belowground respiration (Rsoil), and canopy respiration (Rcanopy) were regularly determined with closed dynamic CO2 exchange systems, and the whole-growing season C-balance was reconstructed by relating these components to potentially controlling factors (green cover, soil moisture, radiation, soil and canopy temperature, and thawing depth). Thawing depth and green cover increased in heated plots, while soil moisture was not significantly affected. Pgross increased 24.2%, owing to both a green cover and a physiological influence of warming. Belowgroun...

This paper discusses the optimisation of a high performance, low cost 0.13 μm CMOS technology with a view on its further scaling to the 100 nm technology node. The focus is mainly on gate oxide (thickness and nitridation method), deep junction implants and annealing. It is shown that in order to take the full benefit of gate oxide thinning, low energy boron implants and spike rapid thermal anneal are mandatory for pMOS devices. The same route gives also promising results for nMOS transistors when gate predoping is used to reduce gate depletion.

Free layers with double MgO/CoFeB interfaces are an established solution for improving the thermal stability at small device dimensions in perpendicular spin transfer torque-magnetic random access memory devices. A thin spacer layer, composed usually of Ta, W, Hf, etc., is used to ease crystallization and improve the perpendicular magnetic anisotropy. Here, we use ferromagnetic resonance to evaluate the impact of Ta or W containing spacer layers on the intrinsic anisotropy Hk and damping α parameters. While both spacer materials enable similar tunnel magneto-resistance and anisotropy values, W typically generates a higher damping. Ta-based spacers are therefore likely better candidates for very low switching current applications.

MTJ stack is optimized for TMR at low RA region, high PMA and 400oC post annealing capability. Atomic level smooth bottom electrode with 0.5A roughness was developed and positive effects on annealing capability and PMA was demonstrated. The scaling challenge of STT-MRAM read operation down to sub-10nm is discussed. Various contributing factors to the MTJ cell resistance variation were investigated with focus on MRAM cell variation due to advanced lithography patterning techniques. With SADP or DSA, the MRAM cell size can be scaled down to 18nm physical dimension with 4.2% σ/μ cell area variation, good enough for sub-10nm technology node.

The scaling challenges of STT-MRAM read operation down to sub-20nm is discussed. Various contributing factors to the MTJ cell resistance variation were investigated with focus on MRAM cell variation due to lithography patterning technique and interconnects. With EUV SADP or single print process, the MRAM cell size can be scaled down to 18nm physical dimension with 4.2% sigma/ave cell area variation. For interconnects, the increasing resistance variation with shrinking dimensions poses most of the challenges.

The aim of this paper is to study the impact of the nitridation techniques on the 1/f noise performances of dual gate 0.18 μm CMOS transistors. Nitrogen is often introduced to prevent boron penetration in ultrathin oxides especially when BF2 is used for the PMOS junction implantation, but as a result the MOS transistor exhibits higher 1/f noise because of the increased fixed trap density. We show how the nitridation process can be improved in terms of 1/f noise characteristics, in a fully integrated technology. Projections of the 1/f noise behaviour for different technologies are also shown, to emphasise how the 1/f noise becomes an issue when other downscaling properties are considered for analog/RF CMOS applications.

Some recent findings in the area of wafer cleaning and thin oxide properties are presented in this paper. Results are shown for a practical implementation of a simplified cleaning concept that combines excellent performance in terms of metal and particle removal with low chemical and DI-water consumption. The effect of organic contamination on ultrathin gate-oxide integrity is illustrated, and the feasibility of using ozonated DI water as an organic removal step is discussed. Metal outplating from HF and HF/HCI solutions is investigated. Also, the final rinsing step is critically evaluated. It is demonstrated that Si surface roughness without the presence of metal contaminants does not degrade gate-oxide integrity. Finally, some critical remarks on the reliability measurements for ultrathin gate oxides are given; it is shown that erroneous conclusions can be drawn from constant-current charge-to-breakdown measurements.

In this paper, results obtained on nickel silicidation and nickel-platinum silicidation in a RTA system based on conductive heating are presented. It is shown that with the Levitor system, it is possible to obtain silicide uniformities

In this letter, nMOSFETs using a NiSi:Yb fully silicide (FUSI) electrode are demonstrated for the first time. We report that the integration of NiSi:Yb FUSI into our reference n-FETs with the respective SiON / HfSiON gate dielectrics results in a Vt reduction from 0.55/0.52 down to 0.30/0.43 V, without degradation of the gate dielectric integrity, channel interface states, and long channel device mobility