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In assisted reproduction, a successful outcome is closely associated with the selection of potentially implantable. culture has its own merits that it can possibly eliminate the selection of non-viable embryos, can mimic physiology with better embryo-uterine and the extended culture can also assess the embryos post-embryonic activation. Scoring of characteristics can also aid in single embryo transfers (SET), reducing the risks of multiple pregnancies. The morphological assessment can serve as a non-invasive tool for better prediction of the outcome in IVF. The two important morphological parameters of grading the inner cell mass (ICM) and the (TE) other than the expansion of the cavity. Various groups reported the importance of either characteristic predicting implantation, pregnancy and live birth. In this retrospective study, we have evaluated which one of these parameters possess the predictive ability of implantation and pregnancy. The embryos frozen as following morphological scoring in the stimulated cycles were replaced in subsequent cycles. The transferred with known implantation were grouped into four different combinations of grades of ICM and TE and analyzed for the association with the clinical pregnancy and the findings were statistically validated. This study demonstrates there is a significant correlation between the grades of TE cells and the clinical pregnancy, so TE grade possibly is a better predictor of in transfers. The grades of embryo can be used as a selection tool for a better IVF outcome.

The laboratory induced cellular stress on zygotes and embryos in their microenvironment could negatively influence the clinical outcome. One of the core components of an IVF lab is the culture incubator. Incubators can provide a stable and appropriate-culture environment by regulating optimal conditions on parameters such as temperature, gas levels and humidity. Clinical studies which compare incubator characteristics may provide insight to their efficacy. In humid conditions of the tropical climate, the incubators without humidifiers can also be used. Hence this study was done to identify the role of a humidifier in a tropical country. In this multicentre retrospective study, embryos from a total of 787 patients were cultured as two groups -A and B in two different types of incubators- humidified and dry, respectively. 647 patients in group A and 140 patients in group B were examined for the developmental parameters. The embryos were frozen at the blastocyst stage and replaced in subsequent frozen embryo transfer cycles. The resulted pregnancy, miscarriage and the clinical pregnancy outcomes were compared. The data was subjected to statistical validation. There was no significant difference observed in the clinical pregnancy rates between the groups. This study validates the possible use of dry incubators for the in vitro culture of human embryos in tropical climate without aiding any humidification.

As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defects may result in functional and delay-related circuit failures. The number of test escapes grows when technology is downscaled. Small delay defects (SDDs) and hidden delay defects (HDDs) are of critical importance in industries today since they are the source of most test escapes and reliability problems. Improving test quality and creating new test methods, algorithms, and test designs requires a comprehensive study of these delay defects. This article reviews the effect and impact of SDD and HDD in logic circuits. It also analyzes the relevant fault models, automatic test pattern generation (ATPG) methods, faster-than-at-speed testing (FAST), cell-aware (CA) based delay tests, test quality metrics, diagnosis of SDDs and HDDs, and commercially available Electronic Design Automation (EDA) tools. Based on the analysis, the benefits and drawbacks of several accessible approaches are addressed.

The world is going digital, this application could be a drop of the digital ocean. This application integrates Digital Locker and all government services. The Digital Locker helps to store all the documents safely and using this app one can easily apply to almost all the government services. As it is an integrated app, the documents that are needed for the application are fetched directly from the Digital Locker instead of uploading it each and every time. This application reduces time complexity, as all the services, and documents are available at one place itself and this can be used for dual purpose.

Communication of images has become very easy and frequent due to popularity of internet. But this fast moving world is prone to various threats from unauthorized users. To protect images and maintain privacy of data many data hiding and encryption techniques are developed. In this paper, a novel reversible 2-stage data hiding algorithm with chaotic based encryption using DNA encoding is proposed. Firstly, Integer Wavelet Transform (IWT) is applied on cover image to convert it from spatial to transform domain. Then, 1st level of data hiding is carried out using threshold based histogram shifting algorithm. Resultant image is interpolated to double of its size and second level of data hiding is done using adaptive prediction error expansion. This stego image is scrambled using chaotic logistic map, result is then DNA encoded using complementary rules. The encoded image is then XOR with a key image generated using hash function and chaotic map. Finally, encrypted image is obtained by DNA decoding the image. Simulation results obtained show the algorithm gives good embedding capacity; also the encrypted images are validated against key sensitivity, statistical and differential attacks

In this paper, we present a hybrid X-filling and two-stage test data compression (TS-TDC) techniques for digital VLSI circuits to reduce the test power and test data volume respectively. The proposed hybrid X-filling combines adjacent filling and modified 4m filling technique to reduce the switching activities of the scan cells. It divides the unspecified bits present in the test cubes by multiples of 4 to increase the correlation between the consecutive test patterns which in turn provides better run length for test data reduction. The filled test cubes are encoded with two stage test data compression in order to reduce test data volume. In the first stage, the completely specified test sets are encoded using Alternative Statistical Run Length (ASRL) coding to enhance the test data compression. The compressed ASRL test set is encoded further using Run Length based Huffman Coding (RLHC) since ASRL codewords contain the maximum run length of oneâ;;s. Experimental results show that the proposed hybrid filling provides the scan-in average and peak-power transition reduction of 88% and 29% respectively against original test sets. The two-stage test data compression scheme achieves a maximum of 86% and an average of 76% compression ratio for ISCAS’89 benchmark circuits.

Compensating the error using additional circuitry is mandatory in a low-error fixed-width multiplier. Instead of compensating the error, reconfiguring n-bit fixed-width multiplier to n/2-bit error-free full-width multiplier using decomposed multiplication is proposed in this paper. The decomposed block multiplication using an area-efficient New Bit Pair Recoding (NBPR) algorithm in fixed-width mode shows a relatively lesser truncation error than existing truncated multipliers. Reconfigurable 16x16 NBPR multiplier in three different modes (8x8, 16x8,16x16) with a fixed 16-bit product is verified on the TSMC 65nm CMOS standard cell library. The experimental results show that the NBPR multiplier consumes a lesser area than standard Booth multipliers. Evaluating the proposed multiplier in imaging shows improved PSNR with minimal error compared to other fixed-width multipliers

Reversible logic is one of the promising research areas in low power applications such as quantum computing, optical information processing and low power CMOS design. In this paper we present a reversible carry look ahead adder and an array multiplier. The circuits are designed such that they result in less garbage outputs, constant inputs, and less gate count compared to previous existing designs. We also gain better improvements in terms of power and area when compared to conventional adders and multipliers. The implemented designs are simulated using NC launch and synthesized by RTL compiler. Keywords Reversible, Garbage constant, Garbage output. 1. INTRODUCTION Power dissipation is one of the important problems faced now a day in VLSI design [4]. The combinational circuit dissipates KTlog 2 [1] Joules of heat for every bit of information to be lasted, irrespective of the technology used .where K is Boltzmann constant and T is temperature. Heat dissipation reduces the life span of the circuits. The information is lost when input bits are not able to recover from the output vectors. Reversible gates naturally take care of heat, since input vectors are uniquely recovered from the output vectors. That is there is one-to-one correspondence between input vectors and output vectors. Each output of the Reversible gates is used once, that is the Reversible circuit is feedback free. Some of the terms related to Reversible logic are [2, 3].