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In this paper, we report multi-threshold-voltage (multi-Vt) options for stacked Nanosheet gate-all-around (GAA) transistors. V t can be modulated through workfunction metal (WFM) thickness as well as the inter-nanosheet spacing (T sus ), the combination of which may be leveraged to increase the number of undoped V t offerings within a CMOS device menu relative to a FinFET CMOS device menu, which fundamentally does not have T sus as a V t tuning option. Hence we propose our multi-V t scheme by taking advantage of the unique structure of stacked GAA transistor.

Multi-channel gate all around (GAA) semiconductor devices march closer to becoming a reality in production as their maturity in development continues. From this development, an understanding of what physical parameters affecting the device has emerged. The importance of material property characterization relative to that of other physical parameters has continued to increase for GAA architecture when compared to its relative importance in earlier architectures. Among these materials properties are the concentration of Ge in SiGe channels and the strain in these channels and related films. But because these properties can be altered by many different process steps, each one adding its own variation to these parameters, their characterization and control at multiple steps in the process flow is crucial. This paper investigates the characterization of strain and Ge concentration, and the relationships between these properties, in the PFET SiGe channel material at the earliest stages of processing for GAA devices. Grown on a bulk Si substrate, multiple pairs of thin SiGe/Si layers that eventually form the basis of the PFET channel are measured and characterized in this study. Multiple measurement techniques are used to measure the material properties. In-line X-Ray Photoelectron Spectroscopy (XPS) and Low Energy X-Ray Fluorescence (LE-XRF) are used to characterize Ge content, while in-line High Resolution X-Ray Diffraction (HRXRD) is used to characterize strain. Because both patterned and un-patterned structures were investigated, scatterometry (also called optical critical dimension, or OCD) is used to provide valuable geometrical metrology.

With the increasing prevalence of complex device integration schemes, tri layer patterning with a solvent strippable hardmask can have a variety of applications. Spin-on metal hardmasks have been the key enabler for selective removal through wet strip when active areas need to be protected from dry etch damage. As spin-on metal hardmasks require a dedicated track to prevent metal contamination, and are limited in their ability to scale down thickness without comprising on defectivity, there has been a need for a deposited hardmask solution. Modulation of film composition through deposition conditions enables a method to create TiO2 films with wet etch tunability. This paper presents a systematic study on development and characterization of PEALD deposited TiO2-based hardmasks for patterning applications. We demonstrate lithographic process window, pattern profile, and defectivity evaluation for a tri layer scheme patterned with PEALD based TiO2 hardmask and its performance under dry and wet strip conditions. Comparable structural and electrical performance is shown for a deposited vs a spin-on metal hardmask.

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

Self-Aligned Quadruple Patterning (SAQP) is a promising technique extending the 193-nm lithography to manufacture structures that are 20nm half pitch or smaller. This process adopts multiple sidewall spacer image transfers to split a rather relaxed design into a quarter of its original pitch. Due to the number of multiple process steps required for the pitch splitting in SAQP, the process error propagates through each deposition and etch, and accumulates at the final step into structure variations, such as pitch walk and poor critical dimension uniformity (CDU). They can further affect the downstream processes and lower the yield. The impact of this error propagation becomes significant for advanced technology nodes when the process specifications of device design CD requirements are at nanometer scale. Therefore, semiconductor manufacturing demands strict in-line process control to ensure a high process yield and improved performance, which must rely on precise measurements to enable corrective actions and quick decision making for process development. This work aims to provide a comprehensive metrology solution for SAQP. During SAQP process development, the challenges in conventional in-line metrology techniques start to surface. For instance, critical-dimension scanning electron microscopy (CDSEM) is commonly the first choice for CD and pitch variation control. However, it is found that the high aspect ratio at mandrel level processes and the trench variations after etch prevent the tool from extracting the true bottom edges of the structure in order to report the position shift. On the other hand, while the complex shape and variations can be captured with scatterometry, or optical CD (OCD), the asymmetric features, such as pitch walk, show low sensitivity with strong correlations in scatterometry. X-ray diffraction (XRD) is known to provide useful direct measurements of the pitch walk in crystalline arrays, yet the data analysis is influenced by the incoming geometry and must be used carefully. A successful implementation of SAQP process control for yield improvement requires the metrology issues to be addressed. By optimizing the measurement parameters and beam configurations, CDSEM measurements distinguish each of the spaces corresponding to the upstream mandrel processes and report their CDs separately to feed back to the process team for the next development cycle. We also utilize the unique capability in scatterometry to measure the structure details in-line and implement a “predictive” process control, which shows a good correlation between the “predictive” measurement and the cross-sections from our design of experiments (DOE). The ability to measure the pitch walk in scatterometry was also demonstrated. This work also explored the frontier of in-line XRD capability by enabling an automatic RSM fitting on tool to output pitch walk values. With these advances in metrology development, we are able to demonstrate the impacts of in-line monitoring in the SAQP process, to shorten the patterning development learning cycle to improve the yield.

FinFET is a promising device candidate for 14nm node CMOS technology. We have developed FinFET device showing superior short channel control at 25nm gate length. This FinFET device featuring gate first high-k/metal gate and merged Epi source/drain process. Key process improvements to resolve the FinFET unique challenges are presented. High drive currents have been obtained for both nFET and pFET. All these results show FinFET is the most promising candidate for 14nm node CMOS technology.

Fully depleted SOI (FDSOI) is a viable option for continued CMOS scaling. In this paper, we overview key challenges for designing and manufacturing extremely thin SOI (ETSOI) devices and provide solutions to each challenge. We demonstrate successful fabrication of ETSOI devices with physical gate length down to 25nm and SOI channel thickness down to 3.5nm. Our highly scaled ETSOI devices exhibit excellent electrostatics and respectable performances. We further discuss unique opportunities enabled by ETSOI for reducing CMOS process complexity and therefore reducing process cost, which in turn at least partially offsets the higher cost of SOI substrates. The unique advantages of ETSOI in conjunction with the presented solutions to challenges render ETSOI a strong candidate for scaling planar CMOS to 22-nm node and beyond.

The performance of low-k nitride spacer etch processes for fin-field effect transistor device fabrication was investigated using C4H9F based and CH3F based plasma gas chemistries. C4H9F showed a larger process window of O2 gas flow rate to obtain infinite etch selectivities of blanket SiN/SiO and SiN/poly-Si than CH3F. The etch selectivity increased in both gases with the reduction of duty cycle in synchronously pulsed plasmas. Low-k spacer formation using a 60-nm gate pitch testsite was demonstrated resulting in the minimized fin recess of 4.7 nm using C4H9F-O2-He plasma at a duty cycle of 30%. This was 2.2 times smaller than that by the CH3F-He plasma. Fifty percent extended etch time resulted in a fin recess of 5.1 nm, suggesting self-limiting behavior using C4H9F-O2-He plasma chemistry. Gap structure analysis on the blanket films suggested that the selective deposition of fluorocarbon, which enhances the selectivity, is driven by plasma assisted deposition in case of the C4H9F-O2-He plasma. These unique characteristics of C4H9F can facilitate innovative plasma etch processes for nitride-based materials patterning in a wide range of applications.The performance of low-k nitride spacer etch processes for fin-field effect transistor device fabrication was investigated using C4H9F based and CH3F based plasma gas chemistries. C4H9F showed a larger process window of O2 gas flow rate to obtain infinite etch selectivities of blanket SiN/SiO and SiN/poly-Si than CH3F. The etch selectivity increased in both gases with the reduction of duty cycle in synchronously pulsed plasmas. Low-k spacer formation using a 60-nm gate pitch testsite was demonstrated resulting in the minimized fin recess of 4.7 nm using C4H9F-O2-He plasma at a duty cycle of 30%. This was 2.2 times smaller than that by the CH3F-He plasma. Fifty percent extended etch time resulted in a fin recess of 5.1 nm, suggesting self-limiting behavior using C4H9F-O2-He plasma chemistry. Gap structure analysis on the blanket films suggested that the selective deposition of fluorocarbon, which enhances the selectivity, is driven by plasma assisted deposition in case of the C4H9F-O2-He plasma. These uniq...

The implementation of magnetic random access memory (MRAM) hinges on complex magnetic film stacks and several critical steps in back-end-of-line (BEOL) processing. Although intended for use in conjunction with silicon CMOS front-end device drivers, MRAM performance is not limited by CMOS technology. We report here on a novel test site design and an associated thin-film process integration scheme which permit relatively inexpensive, rapid characterization of the critical elements in MRAM device fabrication. The test site design incorporates circuitry consistent with the use of a large-area planar base electrode to enable a processing scheme with only two photomask levels. The thin-film process integration scheme is a modification of standard BEOL processing to accommodate temperature-sensitive magnetic tunnel junctions (MTJs) and poor-shear-strength magnetic film interfaces. Completed test site wafers are testable with high-speed probing techniques, permitting characterization of large numbers of MTJs for statistically significant analyses. The approach described in this paper provides an inexpensive means for rapidly iterating on MRAM development alternatives to converage on an implementation suitable for a production environment.

With the increasing prevalence of complex device integration schemes, trilayer patterning with a solvent strippable hardmask can have a variety of applications. Spin-on metal hardmasks have been the key enabler for selective removal through wet strip when active areas need to be protected from dry etch damage. As spin-on metal hardmasks require a dedicated track to prevent metal contamination and are limited in their ability to scale down thickness without compromising on defectivity, there has been a need for a deposited hardmask solution. Modulation of film composition through deposition conditions enables a method to create TiO2 films with wet etch tunability. This paper presents a systematic study on development and characterization of plasma-enhanced atomic layer deposited (PEALD) TiO2-based hardmasks for patterning applications. We demonstrate lithographic process window, pattern profile, and defectivity evaluation for a trilayer scheme patterned with PEALD-based TiO2 hardmask and its performance under dry and wet strip conditions. Comparable structural and electrical performance is shown for a deposited versus a spin-on metal hardmask.

In this paper, a 1D numerical, time-dynamic, fluid model (SHEATHSIM) has been developed to study the effect of RF chuck bias on high density electronegative discharges especially under conditions of sheath inversion and negative ion extraction. In each sheath, ion momentum conservation and ion continuity equations, closed by Poisson's equation, are solved for a given set of bulk densities, temperatures and mean free path lengths of each ionic species. Two such sheaths are closed by a common bulk potential and current continuity. Qualitatively, high electronegativities , low electron temperatures , high asymmetries , DC coupling of bias power and low frequencies tend to favour sheath inversion and subsequent negative ion extraction. Quiescent floating sheath simulations show the self-consistent rise of the plasma regions and the Bohm criterion. Such modelling in conjunction with source antennae electromagnetics and chemical kinetics can lead to computer aided process and reactor design with a view to reducing charge-up damage through negative ion extraction.

A first time rigorous experimental study of effective current (Ieff) variability in high-volume manufacturable (HVM) 14nm Silicon-On-Insulator (SOI) FINFETs is reported which identifies, threshold voltage (Vtlin), external resistance (Rext), and channel trans-conductance (Gm) as three independent sources of variation. The variability in Gm, Vtlin (AVT=1.4(n)/0.7(p) mV-μm), and Ieff exhibit a linear Pelgrom fit indicating local variations, along with non-zero intercept which suggests the presence of global variations at the wafer level. Relative contribution of Gm to Ieff variability is dominant in FINFETs with small number of fins (Nfin); however, both Gm and Rext variations dominate in large Nfin devices. Relative contribution of Vtlin remains almost independent of Nfin. Both n and p FINFETs show the above mentioned trends.

Underlayers (UL), such as organic planarizing layers (OPLs) or spin-on carbon (SOC) layers, play a very important role in various integration schemes of chip manufacturing. One function of OPLs is to fill in pre-existing patterns on the substrate, such as previously patterned vias, to enable lithographic patterning of the next level. More importantly, OPL resistance to reactive ion etch (RIE) processes used to etch silicon-containing materials is essential for the successful pattern transfer from the resist into the substrate. Typically, the pattern is first transferred into the OPL through a two-step RIE sequence, followed by the transfer into the substrate by a fluorine-containing RIE step that leaves the OPL pattern mainly intact. However, when the line/space patterns are scaled down to line widths below 35 nm, it was found that this last RIE step induces severe pattern deformation ("wiggling") of the OPL material, which ultimately prevents the successful pattern transfer into the substrate. In this work, we developed an efficient process to evaluate OPL materials with respect to their pattern transfer performance. This allowed us to systematically study material, substrate and etch process parameters and draw conclusions about how changes in these parameters may improve the overall pattern transfer margin.

Relatively electron-free, positive- and negative-ion (ion–ion) plasmas have been achieved in the afterglow of pulsed-power Cl2 discharges. The application of a pulsed dc bias phase locked to the source power modulation and exclusive to the ion–ion plasma, allows selective bombardment by positive (Cl2+) or negative (Cl−) ions onto a silicon substrate. This allows an equitable comparison of etching by equal energy ions of both polarities. We find that at 50 eV, Cl2+ etches twice as fast as Cl−.

Relatively electron-free positive- and negative-ion plasmas (ion–ion plasmas) have been achieved in the afterglow of pulsed-power Cl2 discharges. The application of a low-frequency (20 kHz) bias voltage phase locked to the source power modulation and synchronous with the ion–ion plasma, resulted in alternating fluxes of positive (Cl2+) and negative (Cl−) ions on a substrate. These results qualitatively agree with a one-dimensional fluid model. This technique to produce alternate irradiations could be used to reduce differential charging-induced damage in high-aspect-ratio etching processes.

In order to extend the optical lithography into sub-72 nm pitch regime, spacer defined double patterning as a self-aligning process option was investigated. In the sidewall defined spacer process, spacer material was deposited directly on the resist to achieve process simplification and cost effectiveness. For the spacer defined double patterning, core mandrel CD uniformity is proven to be a main contributor to pitch-walking and defined a new lithographic process window. Here, the aerial image log-slope is shown to be a measurable predictor of CD uniformity and sidewall angle of the resist pattern. Through resist screening and illumination optimization, resist core-mandrel of 2.5 nm CD uniformity across a focus range more than 200 nm with ± 3.5 % exposure latitude was developed having sidewall control close to the normal. Finally etch revealed that pitch-walking post pitch split can be suppressed below 2 nm within ± 2.5 % exposure latitude.

We have demonstrated a robust magnetic tunnel junction (MTJ) with a resistance-area product RA=8 Omega-mum2 that simultaneously satisfies the statistical requirements of high tunneling magnetoresistance TMR > 15sigma(Rp), write threshold spread sigma(Vw)/

Time-resolved measurements of pulsed discharges can provide information on how negative ions can be used for surface processing. Negative ions are ordinarily trapped inside the plasma volume, but pulsed plasmas allow for efficient negative ion extraction during the afterglow period because the negative ion to electron concentration ratio can increase dramatically. In addition, high-density sources can facilitate negative ion extraction because of their thin sheaths and remote position with respect to the processing wafer. In either case, the first negative ions to reach a processing surface are likely to have crossed the bulk of the sheath region as electrons and attached near the surface.