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As CMOS technology scales down the susceptibility of integrated circuits to radiation effects makes them vulnerable to single-event upsets (SEUs) that may cause the formation of soft errors. In nanometer technologies, SEUs have the potential to impact many nodes within a circuit, resulting to Multiple Node Upsets (MNUs). Several techniques have been proposed to deal with SEUs that simultaneously influence either one, two, or three nodes. This paper presents a latch design that is capable of tolerating up to triple-node upsets (TNUs). Hardware redundancy is exploited to store data in many nodes inside the latch, along with a multiple feedback scheme that provides the recovery of the correct latch state in the case of SEUs. The proposed method provides faster recovery time after an SEU, and at the same time reduced power-delay and area-power-delay products with respect to existing solutions in the literature. [ABSTRACT FROM AUTHOR]

Integrated circuits (ICs) are a keystone for most critical applications operating in high-level radiation environments, spanning from high-energy nuclear applications up to space applications. The long-term reliability of these applications is essential for safe operation. However, the radiation effects for ICs are commonly investigated using fresh circuits, leaving the coupled effect of radiation and aging degradation unknown. This article investigates the impact of negative bias temperature instability (NBTI) aging degradation mechanism on the heavy-ion single event upset (SEU) radiation susceptibility of 28-nm ultra-thin body and buried oxide (UTBB) fully depleted silicon on insulator (FD-SOI) technology using a custom-designed test vehicle. NBTI aging degradation mechanism has been experimentally proven to increase the SEU sensitivity up to $2\times $ for 28-nm UTBB FD-SOI flip-flops. A comprehensive framework is presented to analyze the underlying mechanisms for the impact of NBTI, which includes NBTI aging mechanism modeling, SEU SPICE simulation, TCAD irradiation simulation, and Monte-Carlo simulation of radiation effects. The framework offered a quantitative prediction of the effect of NBTI degradation mechanism on the heavy-ion SEU radiation sensitivity. [ABSTRACT FROM AUTHOR]

Static random access memory (SRAM) with an interleaved bitmap design is of special concern for space applications because the interleaving architecture improves the efficiency of error correction code for single-event upsets (SEUs) in a harsh radiation environment. However, most of the interleaving layout is kept unreleased from the manufacturer, and determining the interleaving parameters of an intact SRAM is a challenge for the radiation hardening system. This work proposed a theoretical decryption model of conventional interleaved bitmaps based on the principle of multiple-bit upset (MBU) correlation analysis. The decryption method was practically implemented with a commercial SRAM, and its unknown interleaving architecture was resolved by the spatial correlation and MBU distance upon SEU fault injection attack with 252Cf source. The disclosed interleaving architecture, the subbyte characteristics, and the bit subblock distribution of the device under test (DUT) are in good agreement with the bitmap obtained with SEU mapping of the microbeam. This work demonstrates the valid and robust SRAM layout decryption model and provides a viable approach for evaluating correction efficiency and component reliability in the radiation hardening system. [ABSTRACT FROM AUTHOR]

We study the radiation environment near the terahertz (THz) dump of the CERN Linear Electron Accelerator for Research (CLEAR) electron accelerator at CERN, using FLUktuierende KAskade in German (FLUKA) simulations and single-event upset (SEU) measurements taken with 32-Mbit Integrated Silicon Solution Inc. (ISSI) static random access memories (SRAMs). The main focus is on the characterization of the neutron field to evaluate its suitability for radiation tests of electronics in comparison with other irradiation facilities. Neutrons at CLEAR are produced via photonuclear reactions, mostly initiated by photons from the electromagnetic cascades that occur when the beam is absorbed by the dump structure. Good agreement is generally found between the measured single-event upset (SEU) rates and the expected values obtained from FLUKA simulations and the known SEU response of the ISSI SRAMs to neutrons, while one position is found to be potentially affected by photon-driven SEUs. [ABSTRACT FROM AUTHOR]

Reduced precision redundancy (RPR) is an alternative to triple modular redundancy (TMR) that reduces the area overhead at the expense of minor accuracy loss in case of error. In this work, we propose a Scaled RPR approach for multistage circuits and analyze the error mitigation tradeoffs. As a case study, several fast Fourier transform designs were tested with low-energy protons and fault injection. Experimental results show that the proposed approach achieves error mitigation with good accuracy, while significantly reducing the area overhead with respect to a full precision TMR approach. [ABSTRACT FROM AUTHOR]

This article is a survey of models used for the calculation of proton single-event upset (SEU) cross-sections from heavy-ion data. Models are evaluated using data in the published literature. The best predictions were given by the analytic models with no free parameters. However, in many cases, the models underpredict the measured cross-section, and a lack of precision may prevent a good prediction on a given device. Additionally, the data used to derive the models has not changed significantly over the last 30 years. [ABSTRACT FROM AUTHOR]

Soft errors induced by Single Event Transient (SET) or Single Event Upset (SEU) are a great threat to integrated circuits. To reduce the error rate and improve the reliability of the circuits, we proposed a radiation hardened flip-flop in this paper, namely, Soft Error Detection and Recovery flip-flop (SEDR-FF). Error detection is based on delayed sampling and redundant storage by a redundant latch. A pulsed clock is adopted to control the redundant latch to reduce the hold time constraint of the latch. To generate the pulsed clock, two efficient delay elements are presented in this paper. Error recovery is accomplished by reloading the previous data stored in a history latch. Transistor-level simulations and timing-annotated gate-level simulations under 65 nm technology show that the proposed flip-flop can efficiently detect and correct the soft errors caused by SET or SEU. It has low overhead of setup time, and is suitable for high-performance designs. In addition, compared with other radiation hardened cells, the proposed flip-flop has moderate power and area overhead, and has lower area cost for fixing hold time violations in circuits designs. [ABSTRACT FROM AUTHOR]

For advanced technology nodes, the static random access memories (SRAMs) are highly vulnerable to the single-event upsets (SEUs), especially the multiple cell upsets (MCUs), by a high-energy ion strike, which is due to the small transistor size and close proximity of the sensitive regions. However, the narrow connection between the fin and the bulk region for fin field-effect transistor (FinFET) inhibits the charge collection compared to the planar transistor structure. In this work, heavy-ion tests were conducted for 16-nm bulk FinFET dual-port SRAMs at two high linear energy transfers (LETs) of 60 and 85 MeV $\cdot $ cm2/mg. The non-saturating behavior of the SEU cross sections and event cross sections for a bit cell is observed even over the LET of 60 MeV $\cdot $ cm2/mg due to the expanding of the sensitive area surrounding the array and the cutting-off area in the FinFET SRAM cells. The distribution curves of the MCU event probabilities for different MCU cluster sizes show that the single-bit upset (SBU) occupies the largest probability of all the single-event cluster sizes, which exhibits the inhibition capability of the Fin structure against the upsets induced by high-energy particles. The parasitic bipolar effect (PBE) is also serious for 16-nm FinFET SRAMs as former planar SRAM, but the charge-sharing effect is effectively inhibited due to the narrow connection between the fin and the bulk region for FinFET. Results presented in this article will help designers estimate the error correcting code (ECC) and interleaving design parameters for radiation-hardened SRAM designs at the 16-nm FinFET process. [ABSTRACT FROM AUTHOR]

As the safety-critical applications (e.g., automotive and medical electronics) emerge, various techniques of radiation hardening by design (RHBD) are proposed to deal with soft errors. Among all RHBD techniques, Built-In Soft-Error Resilience (BISER) is the first one to apply the delayed latching to separate input signals on all flip-flops for error detection. However, the delay values induced by BISER extend the setup time of all flip-flops, and may fail to meet the timing specification of the design. For minimizing such delay impact on the setup time of each flip-flop, we propose the Automated Latching-Delay Assignment (ALDA) to transfer partial values to the CK-Q delay. Later, Time-Borrowable D-Flip-Flop (TBD-FF) as well as a modified design flow is also proposed to realize the delay assignment by ALDA and to complete the design hardening. Experiments show that ALDA together with TBD-FF effectively protects five benchmark circuits against soft errors, and optimally avoids the timing violations caused by the prior delayed-latching solutions. [ABSTRACT FROM AUTHOR]

The high processing power of GPUs makes them attractive for safety-critical applications, where transient effects are a major concern, and resilience must be enforced without compromising performance. Configurable softcore GPUs are a recent technology that allows detailed reliability assessment capable of bringing directions to the design of reliable GPU applications. This work investigates the reliability of the register files and the pipeline of a softcore GPU under radiation-induced faults. It proposes software-based fault tolerance techniques to mitigate errors. Faults are simulated at the register transfer level in four case-study algorithms, and the Architectural Vulnerability Factor (AVF) and Mean Workload to Failure (MWTF) are checked over different GPU configurations. Results indicate that software-based techniques efficiently reduce AVF. In terms of MWTF, results show that the best cases depend on an optimized balance between GPU configuration, application runtime, and AVF. [ABSTRACT FROM AUTHOR]

This work introduces a numerical method to iteratively extract parameters of a rectangular parallelepiped (RPP) sensitive volume (SV) from experimental proton direct ionization (PDI) SEU data. The method combines two separate numerical models. The first model estimates the average linear energy transfer (LET) values for energetic ions, including protons and also heavy ions, in elemental solid targets. The second model describes the statistical variance in the energy deposition events of projectile-induced primary ionization within an RPP-shaped target volume. To benchmark the method, simulated cross section values based on RPP parameters derived with this method are compared with the literature data from four SRAM devices. The RPP geometries determined by this method reproduced the experimental cross section values in the literature with good accuracy, therefore showing that this method can be used to reliably and quickly determine the RPP parameters for SVs in memories sensitive to PDI. The method is currently strictly limited to direct ionization effects, i.e., not taking into account any nuclear reaction mechanisms, and elemental materials due to the underlying models’ definitions. [ABSTRACT FROM AUTHOR]

Static random access memories (SRAMs) are prone to a single-event upset (SEU), also known as soft errors, due to transient noise caused by a single strike of radiation. Beam testing has been extensively used to measure the SEU cross section of SRAMs as a function of the linear energy transfer (LET) of charged particle radiation. The evolution of the cross section as a function of LET is called the cross section curve, which plays a vital role in upset rate analysis for hardness assurance. Various analytical models have been developed to describe SRAM SEU cross section curves, and they have proven to be useful in reducing the cost of beam testing as well as revealing the physics behind test results. However, they involve arbitrary parameters, which make it challenging to predict cross section curves without any beam results. Moreover, the current method of analyzing cross section curves or the LET dependence of cross sections relies on a model different from that is used in the analysis of power-supply-voltage dependence, which is becoming increasingly important because of the demand for low-power operation. To overcome these problems, this article proposes a unified equation that describes both LET and the power-supply-voltage dependence of SRAM SEU cross sections. It comprises only parameters that are physically clear and familiar to SEU researchers. As well as giving possible constraints, comparisons with data from the literature suggest it can be applied to SRAMs fabricated in bulk and silicon-on-insulator (SOI) processes across generations from the early 1000-nm-scale to the current 10-nm-scale technology nodes. [ABSTRACT FROM AUTHOR]

In this paper, a 10T Soft-Error-Immune SRAM (SIS10T) is proposed for space applications. To gauge the relative performance of SIS10T, it is compared with QUATRO10T, QUATRO12T, QUCCE12T, DICE12T and RHD12T. SIS10T can recover from single-event upsets of both polarities induced at all the sensitive nodes, as well as from single event multi-node upsets induced at its internal node-pair. Furthermore, SIS10T shows (consumes) a $1.66\times $ ($1.65\times $)/ $1.62\times $ ($1.35\times $)/ $1.46\times $ ($1.72\times $)/ $1.09\times $ ($2.06\times $) higher read stability (lower hold power) than QUATRO12T/ QUATRO10T/ QUCCE12T/ DICE12T @ ${V}_{\text {DD}} = 1$ V. It also exhibits the highest write ability. [ABSTRACT FROM AUTHOR]

In the aerospace industry, commercial-off-the-shelf (COTS) static random access memories (SRAMs) are a cost-effective solution for obtaining high performance at the system level, which is difficult to obtain using space-qualified components. In addition, the usage of dynamic voltage scaling (DVS) is commonly used in space environments, where low power consumption is a critical issue. This article presents an analysis of the sensitivity against single-event upsets (SEUs) of various COTS bulk SRAMs and advanced low-power SRAMs (A-LPSRAMs) against proton radiation when using DVS to save power. Experimental results will show clear evidence that the sensitivity to SEUs increases when the power is lowered. Two sets of successive technologies (130-, 90-, and 65-nm bulk SRAMs, and 150- and 110-nm A-LPSRAMs) are evaluated against 15-MeV protons and compared with results of 14-MeV neutrons presented in a previous work. Experimental data are finally compared with analytical simulations obtained by using the multiscales single-event phenomena predictive platform (MUSCA-SEP3) Monte Carlo tool to predict the effect of DVS on the SEE sensitivity on more modern technologies in the ITRS/IRDS roadmap. [ABSTRACT FROM AUTHOR]

Today, the certification process for onboard electro-electronic systems against nonionizing radiation can be considered mature and independent, having its own set of requirements. In turn, the current proposal for this process with regard to ionizing radiation is relatively recent and is in the process of improvement and discussion by industry and regulatory bodies, and presents important differences in approach. In this work these two processes are presented comparatively in detail, pointing out similarities and differences in order to contribute to this ongoing discussion, which should, in the medium term, result in regulation for the effects of ionizing radiation. [ABSTRACT FROM AUTHOR]

Today, the certification process for onboard electro-electronic systems against nonionizing radiation can be considered mature and independent, having its own set of requirements. In turn, the current proposal for this process with regard to ionizing radiation is relatively recent and is in the process of improvement and discussion by industry and regulatory bodies, and presents important differences in approach. In this work these two processes are presented comparatively in detail, pointing out similarities and differences in order to contribute to this ongoing discussion, which should, in the medium term, result in regulation for the effects of ionizing radiation.

Latches areused extensivelyin digital circuits; however, as technology scaling reaches nanometric feature sizes, externally induced phenomena (such as radiation strikes in aerospace applications) may cause a single event upset (SEU) in either single or double nodes. Rather than masking, mitigation of an SEU is effectively achieved by recovering the correct value throughthe design of hardened latches. Using the polarity of the radiation-induced voltage pulse, a stacked design is proposed; this circuit permits to accomplish protection and SEU recovery at reduced overhead and so at substantially improved performance. The first proposed latch (RH-1) recovers all single node upsets and has an extremely low delay in its operation, because this latch propagates data to the output stage though only a transmission gate. The fast operation of RH-1 is utilized in the second latch (RH-2) proposed in this article. RH-2 consists of two RH-1 modules to guarantee that at least two nodes maintain the latched values under the occurrence of a double node upset. Simulation results are provided; they show that RH-1 (recovering all single node upsets and many double node upsets) has the best delay and power-delay-area product (PDAP, as combined metric) among all considered designs and the second-best area and dynamic power dissipation among the recovering schemes, and meanwhile RH-2 (recovering all double node upsets) has the best dynamic power dissipation and PDAP among all considered designs and the best area and delay among recovering schemes. [ABSTRACT FROM AUTHOR]

This work presents a single event double node upset (SEDNU) self-healing (DNUSH) latch to meet the high-robustness requirement of the applications used in a harsh radiation environment. The DNUSH latch is based on dual modular redundancy and mainly employs C-elements and inverters, forming multi-feedback interlocked loops to retain the correct data even after the radiation event. The self-healing capability of the proposed latch is successfully shown by the fault injection simulation using Synopsys HSPICE. Simulation results show that the proposed latch can self-heal from all SEDNUs, consumes low power even for high-speed operations, and has the least power-delay-area product (PDAP) compared to the existing SEDNU resilient latches. The proposed latch offers on average 51.25% improvement in speed, 22.67% saving in power consumption, and 59.74% lower PDAP compared to the existing SEDNU resilient latches. In addition, the sensitivity assessment of the proposed latch against the process, voltage, and temperature (PVT) variations are found to be either low or equivalent to the reference latches. [ABSTRACT FROM AUTHOR]

The static random access memory (SRAM) of an ultralow power system-on-chip (SoC) was tested for single-event upsets (SEUs) using alpha particles and neutron beam sources. The measurements are compared to those of an SRAM-based field-programmable gate array (FPGA), built on a similar technology node. The results reveal opposite trends in the two devices regarding the upsets of the logic states, as well as differences in the dependence of SEU cross section (CS) on the operation voltage. The sensitivity of the SoC SRAM to multiple bit upsets with the different radiation sources is analyzed as well. The results demonstrate that the unique SoC design, which enables complete near/subthreshold operation, does not compromise the SoC bit upset tolerance compared to devices of similar technology node which operate at higher voltages. [ABSTRACT FROM AUTHOR]

Field-programmable gate arrays (FPGAs) are susceptible to radiation-induced effects that can affect more than one memory cell. Radiation-induced microsingle event functional interrupts (micro-SEFIs) are one of such events that can upset several bits at a time. These events need to be studied because they can overcome protection from techniques such as triple modular redundancy (TMR) and error correction codes (ECCs). Extracting these events from radiation data helps to understand if specific resources of the FPGA are more vulnerable and the extent of this vulnerability. This article presents a method based on statistics and fault injection to identify micro-SEFIs from beam-test data in the configuration memory and block RAM (BRAM) of SRAM-based FPGAs. The results show the cross section of these events for the configuration RAM (CRAM) and BRAM for three families of Xilinx SRAM FPGAs gathered throughout three neutron tests. This article also contains data from a fault injection campaign to uncover the possible CRAM source bits causing micro-SEFIs in memory look-up tables (LUTs) of Xilinx 7-series and Ultrascale devices. [ABSTRACT FROM AUTHOR]

This article mainly focuses on the single event function interruption (SEFI) and single event latch-up (SEL) of 90 nm NOR flash memories. Devices were irradiated by ions with different linear energy transfer (LET) values from 12.9 to $65.8~MeV\cdot cm^{2}$ /mg. SEFI observed in the device is further divided into bit SEFI, column SEFI, and sector SEFI by severity of data corruption. Under irradiation with low LET value ions, SEL propagation-like phenomena were observed in this work, which was recognized as the process from local latch-up to global latch-up in the peripheral circuits. The underlying mechanisms for SEFI and SEL in NOR flash are discussed. Results indicate that the radiation-induced transient current should be responsible for SEFI, and different forms of SEFI depend on in which part of the circuit that transient current occurred. Besides, SEL in NOR flash is considered to be triggered from the peripheral circuits. [ABSTRACT FROM AUTHOR]

In advanced technology nodes, SRAM cells, used in the aerospace industry, have become highly susceptible to soft-error. In this brief, a Soft-Error-Aware Read-Decoupled 14T (SAR14T) SRAM cell is proposed for aerospace applications. To assess the performance of the proposed cell, it is compared with other soft-error-aware SRAM cells, like WE-QUATRO, QUCCE12T, RHD12T, RSP14T and RHBD14T. Simulation results show that all the sensitive nodes of SAR14T can reattain their initial states after being impacted by soft-error. Furthermore, the cell is capable of recovering from multi-node upset induced at its internal node-pair. Due to the employment of the read-decoupling technique, SAR14T shows the highest read stability compared to its peers. The proposed cell also proves to be the superior SRAM in terms of write ability and write delay. All these improvements are accomplished at the expense of a slightly longer read delay. [ABSTRACT FROM AUTHOR]

The ATLAS Tile Calorimeter (TileCal) readout link and control daughterboard (DB) is the central on-detector hub of the new TileCal electronics upgrade for the high-luminosity large hadron collider (HL-LHC). The DB, which has undergone gradual redesigns during development, provides the connection between the on- and off-detector electronics via bidirectional fiber-optic links. Two CERN-developed, radiation hard GBTx application specified integrated circuits (ASICs) receive LHC timing signals and configuration commands through 4.8-Gb/s downlinks, which are in turn propagated to the front end through Xilinx Kintex Ultrascale field-programmable gate arrays (FPGAs). The Kintex FPGAs also continuously perform real-time readout and transmission of digitized photomultiplier (PMT) samples, detector control system (DCS) signals, and monitoring data through redundant pairs of 9.6-Gb/s uplinks. The DB design aims at minimizing single points of failure and improving the performance and reliability of the board. Apart from the GBTx devices, the DB design relies on radiation-qualified commercial off-the-shelf (COTS) components. Mitigation of radiation-induced single-event upsets (SEUs) in the FPGAs is performed by a combination of the Xilinx soft error mitigation (SEM) controller and triple-mode redundancy (TMR) schemes in the FPGA firmware. Data integrity is protected through forward error correction (FEC) in the downlinks and cyclic redundancy check (CRC) error verification in the redundant uplinks. This article presents the latest revision of the DB (version 6), a redesign that addresses single-event latch-up (SEL) behavior observed in the Kintex Ultrascale+ FPGAs used in the previous revision, and features a more robust power circuitry combined with an improved current monitoring scheme, enhanced performance of the analog-to-digital converter (ADC) read-out, and improved timing performance. [ABSTRACT FROM AUTHOR]

The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2- $\mu \text{m}$ double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM). The physical mechanism of single-event effect (SEE) is explained through technology computer-aided design (TCAD) simulations. TCAD simulations were also performed to explain the impact of back-gate bias on charge collection and full width at half maximum (FWHM) of the pulsewidth at various temperatures. Both charge collection and FWHM of the pulsewidth increase significantly with temperature rising from 240 to 400 K. It is demonstrated that the SEU threshold linear energy transfer (LET) for a DSOI 6T SRAM cell decreases with an increase in temperature. Compared with a fully depleted SOI (FDSOI) technology, the unique independent back-gate bias scheme for a DSOI SRAM cell exhibits higher tolerance to SEU. At 400 K, it is found that the SEU threshold LET (LETth) for a DSOI 6T SRAM cell increases by 12.5% with back-gate bias of nMOS reduced from 0 to −15 V. [ABSTRACT FROM AUTHOR]

The contribution of Coulomb processes induced by incident electrons in single event upset (SEU) sensitivity is investigated. The case of 65-nm silicon on insulator (SOI) memory is studied. Several orbits (GPS, Jupiter Icy Moons Explorer’s (JUICE’s) orbits) are analyzed. The relative importance to the total SEU rate of electron, proton, and gamma environments is compared. SEU induced by electrons is obtained during Earth missions. In the environment of Jupiter, equivalent SEU sensitivities have been obtained between the studied device and the European Space Agency (ESA) SEU monitor. However, the relative importance of the physical processes involved is very different. Proton-induced SEU rates are estimated about one decade greater than electron-induced SEU rates. The Bremsstrahlung contribution has been found negligible in such an environment. [ABSTRACT FROM AUTHOR]

This article investigates radiation-induced switching mechanisms, temperature effects, breakdown voltage, sensitive volume, and critical charge definitions for spin-transfer torque magnetic tunnel junctions. The thermal spike model is adopted to estimate the temperature reached during heavy-ion irradiation, and temperature effects are suggested to be responsible for the magnetic properties’ degradation and for upset processes. [ABSTRACT FROM AUTHOR]

Radiation-induced multiple-cell upsets (MCUs) are events that account for more than 50% of failures on triple modular redundancy (TMR) designs in SRAM field programmable gate array (FPGA). It is important to understand these events and their impact on FPGA designs to develop improved fault mitigation techniques. This article describes an enhanced fault injection (FI) method for SRAM-based FPGAs that injects MCUs within the configuration memory of an FPGA based on MCU information extracted from previous radiation tests. The improved FI technique uncovers 3 × more failures than is observable in conventional single-bit FI approaches. The results from several MCU FI experiments also show that injecting MCUs can replicate the failures observed in the radiation beam test and identify new failure mechanisms. [ABSTRACT FROM AUTHOR]

This article presents an approach to calculate single-event upset rates using a track structure theory (TST) as an alternative to the rectangular parallelepiped (RPP) model. The TST approach accurately predicts upset rates with fewer parameters than the RPP model, and all parameters are derived from the data. The model also works for device-level effects where there may be an unknown number of sensitive volumes (SVs). In addition to its utility in rate calculations, derivation of the model confirms one of the fundamental assumptions of the RPP model, namely that the ion track can be treated as a line of charge, smaller than the SV. [ABSTRACT FROM AUTHOR]

Upset bitmaps distribution features in SRAM arrays exposed by various types of pulsed ionizing radiation (X-rays, n-γ, laser-accelerated protons) were analyzed by experimental data processing with 2D Walsh-Hadamard transform, i.e. expansion of orthogonal rectangle functions on closed set basis. Using such processing with comparison to expansion on 1D Fourier or Walsh-Hadamard transform allows one to detect additional regularities in upset distribution. The presence of these regularities can be explained by voltage dropdown across integrated circuit voltage supply buses arising under pulsed radiation exposure as a result of dose rate effects. The "stripe-like" upset bitmap is explicitly observed under the pulsed X-ray exposure. In the case of pulsed complex n-γ (fission neutrons) and laser-accelerated protons exposure the dose rate effects significance and therefore the presence of any regularities in upset bitmaps are strongly device-specific. A quantitative criterion was introduced on basis of 2D Walsh-Hadamard amplitude spectra's statistical examination permitting to pick out upset bitmaps with regularities even for visually uniform upset bitmaps. • ARM-based microcontroller was exposed to various types of ionizing radiation. • SRAM upset bitmaps were analyzed with 2D Walsh-Hadamard transform. • The existence of dose rate effects is investigated for the case of pulsed exposure. • The stripe-like upset bitmaps under pulsed exposure explained by voltage dropdown. • Pulsed laser-accelerated protons and n-γ may lead to non-uniform upset bitmaps. [ABSTRACT FROM AUTHOR]

Characterizing low-energy neutrons (<10 MeV)-induced single-event upsets (SEUs) and multiple cells upsets (MCUs) is essential to validate the current standard for terrestrial soft error rate (SER) and investigate its enhancement. Following our preliminary analysis on the contribution of the low-energy neutrons to the total terrestrial SER at the nominal operating voltage of 1.0 V by Liao et al. (2020), this article newly presents and analyzes the data measured at the low operating voltage of 0.4 V. The dependence of SEU cross section on the neutron energy is similar between the operating voltages of 0.4 and 1.0 V, including onset energy of around 6 MeV. The existence of MCUs at 4.1-MeV neutrons was also confirmed at both the operating voltages. Based on the measurement, we approximate the dependence of SEU and MCU cross sections as Weibull functions of the neutron energy. The terrestrial SER of SEUs and MCUs was calculated by folding the Weibull function and the flux spectrum. The calculated result indicates that the SER originating from the low-energy neutrons is less than 6% in the terrestrial environment at New York and Tokyo City. We confirm that disregarding the flux of neutrons below 10 MeV in the acceleration factor calculation at accelerated neutron tests, which follows the current standard defined in JESD89, could give a reasonable SER estimation accuracy for both SEUs and MCUs. On the other hand, for covering the beams having an extremely high proportion of low-energy neutrons, considering the flux of neutrons above 6 MeV would be an option for better SER estimation. [ABSTRACT FROM AUTHOR]

The effects of buried-well potential perturbation under the buried-oxide (BOX) layer are studied in both a heavy-ion single event upset (SEU) test and a high-energy proton-SEU test of a silicon-on-insulator (SOI) dual interlocked storage cell (DICE)-based flip-flop. Their dependence on incident angle and back bias is discussed. We fabricated both DICE-based flip-flop and conventional flip-flop, which are designed as 80 000-stage shift-register chains. In a heavy-ion test, a considerable number of SEUs were observed at back bias exceeding 2.4 V, and a ten-times larger SEU-cross section was finally recorded at back bias of 3.0 V compared with the total active area of a DICE-based flip-flop cell. This marks the first case where DICE topology was found to be broken by buried-well potential perturbation on an SOI DICE-based flip-flop. In a proton test, one error was observed at back bias of 2.0 V. The SEU rate in the Van Allen belt at an altitude of 2300 km and an inclination of 90° was estimated as being once every 5 years. [ABSTRACT FROM AUTHOR]

In space, due to high energy particles, which cause single event upsets (SEUs), the traditional 6T SRAM cell becomes more susceptible to soft-error. In order to address this, a radiation hardened memory-by-design 10T (RHMD10T) SRAM cell is proposed in this brief. The relative strength of RHMD10T is estimated by comparing it with other contemporary cells such as QUATRO10T, QUCCE10T, QUATRO12T, QUCCE12T, NS10T and PS10T over various major design metrics. RHMD10T exhibits 1.09 ×/ 1.16 ×/1.26 × shorter read delay than QUCCE10T/ QUATRO10T/ NS10T. RHMD10T has the highest read stability and can tolerate the highest amount of critical charge than all other comparison cells. RHMD10T consumes the lowest hold power than all other comparison cells, except NS10T. In addition, RHMD10T is the least susceptible to SEU, except QUCCE12T. All these aforementioned improvements of RHMD10T are obtained at a cost of slightly longer write delay and lower write ability. [ABSTRACT FROM AUTHOR]

In this article, a highly reliable radiation-hardened-by-design (RHBD) 10T static random access memory (SRAM) cell is proposed. In space, the impact of alpha particles and cosmic radiation flips the node data resulting in loss of data in conventional 6T SRAM. The proposed SRAM has quad-nodes, which stores the data. The architecture is designed with a quad-latch topology and simulated in 65-nm CMOS technology with a supply voltage of 1.2 V. The result shows that the design can tolerate both 0 to 1 and 1 to 0 single event upset errors on any one of its nodes. The read and write access times of the proposed design are 88.78 and 241.77 ps, respectively. The static noise margin for read, write, and hold operations are 379.01, 906.51, and 637.1 mV, respectively. The proposed architecture takes an area of 6.52 μm. [ABSTRACT FROM AUTHOR]

Space consists of high-energy particles and high-temperature fluctuations, which causes single event upsets (SEUs). Conventional 6T static random access memory (SRAM) is unable to tolerate this harsh environment in space. Therefore, it is necessary to design an SRAM, which can withstand this harsh environment. In order to mitigate SEUs, a radiation-hardened SRAM cell, named soft-error resilient read decoupled 12T (SRRD12T), is presented in this article. To estimate the relative performance of the proposed cell, it is compared with other contemporary designs, such as RHMN12T, RHMP12T, RHD12T, QUCCE12T, and QUATRO12T, over various important design metrics. SRRD12T can not only recover from SEU induced at any of its sensitive nodes but also from single event multi-node upsets (SEMNUs) induced at its storage node pair. Furthermore, due to the read decoupled design of SRRD12T, it exhibits the highest read stability. In addition to these, SRRD12T shows 1.14×/1.17× shorter write delay than RHD12T/RHMP12T. Moreover, SRRD12T consumes lower hold power and exhibits higher write ability than most of the comparison cells. However, these advantages are obtained by exhibiting a slightly longer read delay. [ABSTRACT FROM AUTHOR]

Triple modular redundancy (TMR) is a single-event upset (SEU)-mitigation technique that uses three circuit copies to mask a failure in any one copy. It improves the soft error reliability of designs implemented on SRAM-based field-programmable gate arrays (FPGAs) by masking the effects of upsets in the configuration memory. Although TMR is most effective when applied to an entire FPGA design, a reduction in the sensitive cross section of an FPGA design can be obtained by applying TMR selectively. This article explores several approaches for selecting components to triplicate. The benefit is a reduction in the neutron cross section for any output error as a percentage compared to that of a non-triplicated design. The cost is the percentage of components triplicated. The goal is to maximize the benefit–cost ratio. Twenty-five different selections are tested on a benchmark design. Some selections increase the cross section; others decrease the cross section significantly. [ABSTRACT FROM AUTHOR]

This article presents a static random access memory (SRAM)-based flexible radiation monitor. The monitor was fabricated in a 65-nm CMOS technology and it is designed as an application-specific integrated circuit, which comprises 768k bits SRAM cell matrix with individual power supply and a digital control core with a serial peripheral interface (SPI). By adjusting the core voltage of the SRAM matrix, the radiation sensitivity was made flexible. Also, SRAM cells with different threshold voltages were implemented to get further extension on tunable sensitivity range. The monitor has been tested under heavy ions with a linear energy transfer (LET) from 1.5 to 48.5 $\text {MeV}\cdot \text {cm}^{2}$ /mg, high-energy (50–186 MeV) and low-energy (0.7–5 MeV) protons, and 14-MeV and thermal neutrons. An analysis was performed on how single-event upset sensitivity changes while tuning the supply voltage under different radiation environments. The results show that the monitor has the potential for space and facility applications. [ABSTRACT FROM AUTHOR]

Soft processors are often used within field-programmable gate array (FPGA) designs in radiation hazardous environments. These systems are susceptible to single-event upsets (SEUs) that can corrupt both the hardware configuration and software implementation. Mitigation of these SEUs can be accomplished by applying triple modular redundancy (TMR) techniques to the processor. This article presents fault injection and neutron radiation results of a Linux-capable TMR VexRiscv processor. The TMR processor achieved a $10\times $ improvement in SEU-induced mean fluence to failure with a cost of $4\times $ resource utilization. To further understand the TMR system failures, additional post-radiation fault injection was performed with targets generated from the radiation data. This analysis showed that not all the failures were due to single-bit upsets, but potentially caused by multibit upsets, nontriplicated IO, and unmonitored nonconfiguration RAM (CRAM) SEUs. [ABSTRACT FROM AUTHOR]

In this article, we present the effects of voltage scaling and forward body biasing (FBB) on single-event effect sensitivity of a 28-nm ultra-thin body and box (UTBB) fully depleted silicon on insulator (FD-SOI) technology. Heavy-ion irradiation was performed for single-event upset (SEU) and single-event transient (SET) sensitivity assessment on characterization test chips under three supply voltages, with and without back-gate voltage application. Measurements show a steady SEU sensitivity for any supply voltage across the two FBB configurations, whereas SET sensitivity is diminished under FBB. SPICE and TCAD mixed-mode simulations were run to assess the contribution of electrical factors as well as charge extraction mechanisms. While drive strength is increased under FBB, the bipolar amplification plays an important role in sensitivity at low linear energy transfers (LETs). [ABSTRACT FROM AUTHOR]

The influence of ion track characteristics on single-event upsets (SEU) and multiple-cell upsets (MCUs) is investigated in 65-nm static randon access memory (SRAM) above the heavy-ion linear energy transfer (LET) threshold. The experimental results show that for the incident heavy ions with the same or similar LET but different energies, SEU cross section of low-energy ions is higher than high-energy ions when the LET values are located below the knee point of low-energy SEU event cross section curves. With the LET values increasing above the knee point, SEU cross section of high-energy ions is higher than low-energy ions. When the effective LETs of different-energy ions within the sensitive region are the same, MCU mean, MCU ratio, and MCU event cross sections of high-energy ions are greater than those of low-energy ions due to larger track radius. During the test evaluation of heavy-ion single-event effect (SEE) in nanometer devices, it may be advisable that the SEU LET threshold be obtained with low-energy ions and the SEU saturation cross section be obtained with high-energy ions. [ABSTRACT FROM AUTHOR]

The distribution of single-event upsets (SEUs) in commercial off-the-shelf (COTS) static random access memory (SRAM) has generally been thought to be uniform in a device. However, process-induced variation within a device gives rise to variation within the cell-level electrical characteristic known as the data retention voltage ($V_{\mathrm{ DR}}$). Furthermore, $V_{\mathrm{ DR}}$ has been shown to directly influence the critical charge ($Q_{\mathrm{ C}}$) necessary for stored data to upset. Low-energy proton irradiation of COTS SRAMs exhibits a preference toward upsetting cells with lower $Q_{\mathrm{ C}}$. An electrical procedure is presented to map relative cell critical charge values without knowledge of the underlying circuitry, allowing customized device usage. Given cell-level $Q_{\mathrm{ C}}$ knowledge, a device can have its cells “screened” such that those with low $Q_{\mathrm{ C}}$ are not used to store data. This work presents the results such a screening process has on the SEU per bit cross section. [ABSTRACT FROM AUTHOR]

Single-event upsets are observed in a 72-layer 3-D NAND flash memory operated in a single-level cell mode after low-energy proton (500 keV–1.2 MeV) and heavy-ion irradiation. The layer-by-layer error count is analyzed to visualize the stopping of low-energy protons within the memory stack, and Monte Carlo simulations are correlated with the experimental data. Direct ionization by low-energy protons is identified by 3-D data analysis and the energy dependence of device-sensitive cross section. Heavy-ion data is also presented for comparison. [ABSTRACT FROM AUTHOR]

Convolutional neural networks (CNNs) are quickly becoming an attractive solution for autonomous vehicles, military weapons, and space exploration. Thanks to their reconfiguration ability, design flexibility, and low power consumption, field-programmable gate arrays (FPGAs) have become a promising candidate for CNN accelerators. However, FPGAs have been proven to be susceptible to radiation-induced single-event upsets (SEUs). One goal of this article is to analyze the impact of quantization on the reliability of CNNs in FPGAs. Therefore, we performed quantization on ZynqNet without affecting its classification accuracy. Meanwhile, we implemented the triple modular redundancy (TMR) version of ZynqNet and we also evaluated the effects of SEUs on these CNNs through both fault injections and neutron exposures. Fault injection results show that TMRed ZynqNet reduces the soft error rate (SER) by 33.59% with a circuit area increase of 111.92% when compared with the standard ZynqNet. The experimental results demonstrate that the quantized ZynqNet reduces the SER by 71.36% with a circuit area reduction of 44.76% when compared with the standard ZynqNet. These results confirm that quantization does contribute to SER reduction of the neural networks. In addition, the operating system on the processing system (PS) side was also found to be highly sensitive to SEUs, and, thus, mitigation techniques should be applied. [ABSTRACT FROM AUTHOR]

Static Random Access Memory (SRAM) is primarily used as a memory storage element, which is susceptible to radiation-induced Single Event Upsets (SEUs). Hence, a robust SRAM bit-cell design is primarily a difficult task to address the space radiation environment. Furthermore, as the transistor’s size moves into nanometer regimes, a new challenge like Single Event Multiple Effects (SEME’s) evolved in SRAMs. SEME’s make the design of SRAM a serious challenge. In this article, a novel Radiation Hardened By Design (RHBD) SRAM bit-cell is proposed based on the polarity upset mechanism of SEUs. This work shows that the proposed RHBD14T SRAM bit-cell is SEU immune and delivers higher SEME critical charge than state-of-the-art RHBD SRAM bit-cells. The Monte Carlo (MC) simulations further show that the proposed RHBD14T SRAM delivers the lower Probability of Failure when compared to reported RHBD SRAM cells. Consequently, the proposed bit cell’s sensitive area is 128% lower with respect to the recently reported state-of-the-art RHBD RSP14T SRAM bit-cells. [ABSTRACT FROM AUTHOR]

The history of integrated circuit (IC) development is another record of human challenges involving space. Efforts have been made to protect ICs from sudden malfunctions due to single-event effects (SEEs). These effects are triggered by only a single strike of particle radiation, such as an α-ray or cosmic ray, originating from our solar activity and galactic events including supernovas. This article explores how SEEs have evolved along with the progress in complementary metal-oxide-semiconductor (CMOS) digital IC technology, or device scaling, from the early micrometer-scale generations to the current nanometer-scale generations. For this purpose, focusing on basic digital elements, that is, inverters and static random access memories (SRAMs), this study collected more than 100 sets of data on four characteristic parameters of single-event upsets (SEUs) and single-event transients (SETs), both of which are undesired flips in digital logic states. The results show that all the examined parameters, such as the SEU critical charge, decrease with the device feature size. Analysis involving structure classification, such as bulk versus silicon-on-insulator (SOI) substrates and planar versus fin channels, reveals relationships between the examined SEE parameters and other device features such as the power supply voltage. All the data collected in this survey are explicitly given in tables for future exploration of IC reliability. [ABSTRACT FROM AUTHOR]

In harsh radiation environments, it is well known that the angle of incidence of impinging particles against the surface of the operating devices has significant effects on their sensitivity. This article discusses the sensitivity underestimations that are made if particle isotropy is not taken into account, by means of an analytical study made with a single-event upset predictive platform. To achieve this goal, experimental results carried out with a commercial-off-the-shelf (COTS) bulk 130-nm nonvolatile static random access memory (SRAM) for various incident angles on 14.2 MeV neutrons are first discussed. Then, a modeling tool called multiscales single-event phenomena predictive platform (MUSCA-SEP3) is used to predict the sensitivity of this memory under the same environmental conditions. Predictions and experimental results will be cross-checked, and therefore, the feasibility of this tool will be demonstrated for testing any other incident angle. Finally, an isotropic environment and an XY SRAM array will be emulated with MUSCA in order to demonstrate that the asymmetrical cross sections that were observed experimentally for various incidence angles are due to the underlying asymmetry of the metalization/passivation layers within the device with respect to its active silicon. Conclusions will finally be drawn as for the importance of taking into account particle isotropy in radiation-ground tests. [ABSTRACT FROM AUTHOR]