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The UML Profile for Modeling and Analysis of Real-Time and Embedded systems promises a general modeling framework to design and analyze systems. Lots of works have been published on the modeling capabilities offered by MARTE, much less on available verification techniques. The Clock Constraint Specification Language (CCSL), first introduced as a companion language for MARTE, was devised to offer a formal support to conduct causal and temporal analysis on MARTE models. This work relies on a state-based semantics for CCSL to establish correctness properties on MARTE/CCSL specifications. We propose and compare two different techniques to build the state-space of a specification. One is an extension of some previous work and is based on extended finite state machines. It relies on integer linear programming to solve the constraints and reduce the state-space. The other one is based on an intentional representation and uses pure Boolean abstractions but offers no guarantee to terminate when the specification is not safe. The approach is illustrated on one simple example where the architecture plays an important role. We describe a process where the logical description of the application is progressively refined to take into account the execution platform through allocation. [ABSTRACT FROM AUTHOR]

Massively parallel processor array (MPPA) architectures are becoming widely available computing platforms. Because of formal similarities, they are good candidates for implementing cellular automata (CA). An essential difference still remains regarding the freedom in communications. In MPPA there is a fixed on-chip network interconnection topology but every CA has its own definition of neighbourhood. While a cell in a CA can be considered as directly connected to its neighbours, these connections correspond to paths in the network of the MPPA. The communications need to be routed and scheduled to reach their proper destination. In previous work we introduced a formal data-flow process network model named KRG (for K-periodically Routed Graph). Its main feature is to allow regular switching directives. In the present paper we will use it to represent the proper local sequences of routing directives that will efficiently propagate values from cells to cells so as to implement the required CA neighbourhood. We present the neighbourhood broadcasting algorithm that computes these routing directives. One should note here that the problem is made more complex as data traffic between distinct source and target cells must be merged, while multicast may save a tremendous amount of communications when values are required in multiple locations. We demonstrate the expressive power of our formalism on the case of a 2D CA where the neighbourhood consists of all cells at Moore distance at most n. Further potential applications of our framework are hinted. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents an algorithm to statically schedule live and strongly connected Marked Graphs. The proposed algorithm computes the best execution where the execution rate is maximal and place sizes are minimal. The proposed algorithm provides transition schedules represented as binary words. These words are chosen to be balanced. The contributions of this paper are the proposed algorithm itself along with the characterization of the best execution of any marked graph. [Copyright &y& Elsevier]

The domain of Real-Time Embedded (RTE) systems was ackowledged as being largely influential on many feature additions to the recent UML2.0 standard [Björkander, M., FDL'03 Keynote address, 2003]. Work on UML1.4 Scheduling, Performance & Time (SPT) profile also goes in that direction. Still, the paradigms underlying these modeling efforts are that of software components, running on a real-time OSs with physical time constraints and middleware (e.g., RT-Corba) concerns. In other areas of Embedded System Design other paradigms are at work, owing to codesign techniques at the border between software and hardware, or discrete time mathematical engineering (MATLAB/Simulink) and digital signal processing algorithms, etc. The paradigm of Synchronous Reactive (S/R) systems [Benveniste, A., Berry, G.: The synchronous approach to reactive and real-time systems. Proc. IEEE 79(9), 1270–1282 (1991); Benveniste, A., Caspi, P., Edwards, S., Halbwachs, N., Guernic, P.L., de Simone, R.: Synchronous languages twelve years later. Proc. IEEE 91(1), 64–83 (2003)], with discrete logical time and behavior decomposition into instantaneous reactions, proved quite natural in such areas to model mixed hardware/software System-Level Design (SLD). We describe here some of the modeling paradigms needed for a true S/R model framework, and corresponding diagrammatic interpretations. The synchronous reactive domain described here should be dealt with and included in the forthcoming UML profile for “Modeling and Analysis of Real-Time and Embedded systems” (MARTE), whose request for proposal was recently voted at OMG. [ABSTRACT FROM AUTHOR]

We present SL, a new programming language of the synchronous reactive family in which hypotheses about signal presence/absence are disallowed. One can decide that a signal is absent during an instant only at the end of this instant, and so reaction to this absence is delayed to the next instant. Sources of causal circularities are avoided, while only weak preemption remains. A structural operational semantics is provided through rewrite rules, and an implementation is described. In addition to directly executing programs, this implementation can also be used to produce automata by symbolic evaluation. [ABSTRACT FROM AUTHOR]

Proper control of epithelial morphogenesis is vital to development and is often disrupted in disease. After germ band extension, the cells of the Drosophila ventral embryonic epidermis are packed in a two-dimensional polygonal array. Although epithelial cell rearrangements are being studied productively in several tissues, the ventral epidermis is of particular interest as the final cell arrangement is, uniquely, far from equilibrium. We show that over the course of several hours, a subset of cells within each parasegment adopts a rectilinear configuration and aligns into parallel columns. Live imaging shows that this is accomplished by the shrinkage of select cell interfaces, as three-cell junctions are converted to four-cell junctions. Additionally, we show that non-muscle Myosin II and the polarity proteins Discs large (Dlg) and Bazooka are enriched along cell interfaces in a complex but reproducible pattern that suggests their involvement in junctional conversion and cell alignment. Indeed, depletion of Myosin II or dlg disrupts these processes. These results show that tight spatial regulation of actomyosin contractility is required to produce this high-energy arrangement of cells. [ABSTRACT FROM AUTHOR]

We propose a general method to characterize and synthesize correctness-preserving asynchronous wrappers for synchronous processes on a globally asynchronous locally synchronous (GALS) architecture. While a synchronous process may rely on the absence of a signal to trigger a reaction, sensing absence in an asynchronous environment may be unfeasible due to uncontrolled communication latencies. A simple and common solution is to systematically encode and send absence notifications, but it is unduly expensive at run-time. Instead, our approach is based on the theory of weakly endochronous systems, which defines the largest sub-class of synchronous systems where (possibly concurrent) asynchronous evaluation is faithful to the original (synchronous) specification. Our method considers synchronous processes or modules that are specified by synchronization constraints expressed in a high-level multi-clock synchronous reactive formalism. The algorithm uses a compact representation of the abstract synchronization configurations of the analyzed process and determines a minimal set of synchronization patterns generating by union all its possible reactions. A specification is weakly endochronous if and only if these generators do not need explicit absence information. In this case, the set of generators can directly be used to synthesize the concurrent asynchronous multi-rate wrapper of the process. [ABSTRACT FROM AUTHOR]