2,064 results on '"Simoen, E."'
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2. Novel Y-function based strategy for parameter extraction in S/D asymmetric architecture devices and low frequency noise characterization in GAA Si VNW pMOSFETs
3. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications
4. In-depth static and low frequency noise assessment of p-channel gate-all-around vertically stacked silicon nanosheets
5. DC and low a frequency noise analysis of p channel gate all around vertically stacked silicon nanosheets
6. Gate dielectric material influence on DC behavior of MO(I)SHEMT devices operating up to 150 °C
7. Detailed low frequency noise assessment on GAA NW n-channel FETs
8. Improved physics-based analysis to discriminate the flicker noise origin at very low temperature and drain voltage polarization
9. Low frequency noise analysis on Si/SiGe superlattice I/O n-channel FinFETs
10. Low-frequency noise measurements at liquid helium temperature operation in ultra-thin buried oxide transistors – Physical interpretation of transport phenomena
11. Detailed characterisation of Si Gate-All-Around Nanowire MOSFETs at cryogenic temperatures
12. Bayesian Parameter Estimation
13. Low frequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part II: Measurements and results
14. Low frequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part I: Theory and methodology
15. Model Class Selection for Prediction Error Estimation
16. Recent Trends in Bias Temperature Instability
17. Understanding and optimizing the floating body retention in FDSOI UTBOX
18. Corrigendum to “In-depth static and low frequency noise assessment of p-channel gate-all-around vertically stacked silicon nanosheets” [Solid-State Electron. 201(2023) 10859]
19. (Invited) Defect Engineering for Monolithic Integration of III-V Semiconductors on Silicon Substrates
20. Challenges in ultra-shallow junction technology
21. Identification of Si film traps in p-channel SOI FinFETs using low temperature noise spectroscopy
22. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs
23. Electrical characterization of p-GeSn/n-Ge diodes with interface traps under dc and ac regimes
24. Impact of processing and back-gate biasing conditions on the low-frequency noise of ultra-thin buried oxide silicon-on-insulator nMOSFETs
25. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs
26. Insights into Scaled Logic Devices Connected from Both Wafer Sides
27. Negative Bias Temperature Instabilities induced in devices with millisecond anneal for ultra-shallow junctions
28. Investigation of Tri-Gate FinFETs by Noise Methods
29. SOI MOSFET Transconductance Behavior from Micro to Nano Era
30. Defect assessment and leakage control in Ge junctions
31. In depth static and low-frequency noise characterization of n-channel FinFETs on SOI substrates at cryogenic temperature
32. Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics
33. Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications
34. Electron Spin Resonance Probing of Defects in Si Foils Fabricated by the SLIM-Cut Method
35. Germanium Deep-Submicron p-FET and n-FET Devices, Fabricated on Germanium-On-Insulator Substrates
36. Lateral PIN Photodiode with Germanium and Silicon Layer on SOI Wafers.
37. DC and low frequency noise performances of SOI p-FinFETs at very low temperature
38. Back-Gate Induced Noise Overshoot in Partially-Depleted SOI MOSFETs
39. Radiation Characteristics of Short P- Channel MOSFETs on SOI Substrates
40. Linking Room- and Low-Temperature Electrical Performance of MOS Gate Stacks for Cryogenic Applications
41. Noise and Tunneling Through the 2.5 nm Gate Oxide in Soi MOSFETs
42. Experimental Assessment of Quantum Effects in the Low-Frequency Noise and RTS of Deep Submicron MOSFETs
43. Physics and Modeling of Radiation Effects in Advanced CMOS Technology Nodes
44. DC and low-frequency noise behavior of the conductive filament in bipolar HfO2-based resistive random access memory
45. Study of the impact of doping concentration and Schottky barrier height on ohmic contacts to n-type germanium
46. Influence of γ- Radiation on Short Channel SOI-MOSFETs with Thin SiO2 Films
47. Finding the Chaotization Conditions Through Local Stability Analysis
48. Perspectives of Silicon-on-Insulator Technologies for Cryogenic Electronics
49. Back Gate Voltage Influence on the LDD SOI NMOSFET Series Resistance Extraction from 150 to 300 K
50. Challenges and opportunities in advanced Ge pMOSFETs
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