123 results on '"Sillon, N."'
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2. RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking
3. (Invited) Future Challenges and Diversifications for Nanoelectronics by the End of the Roadmap and Beyond
4. Caractérisation en hyperfréquences et modélisation de Vias Traversant le Silicium pour l'intégration de puces tridimensionnelles
5. 3D Integration challenges today from technological toolbox to industrial prototypes
6. Wafer level underfill entrapment in solder joint during thermocompression: Simulation and experimental validation
7. WSS and ZoneBOND temporary bonding techniques comparison for 80μm and 55μm functional interposer creation
8. Challenges and solutions for ultra-thin (50 μm) silicon using innovative ZoneBOND™ process
9. Characterization and modelling of Si-substrate noise induced by RF signal propagating in TSV of 3D-IC stack
10. Enabling technologies for advanced wafer level camera integration
11. 3D integration demonstration of a wireless product with design partitioning
12. 200mm & 300mm Processes & Characterization for Face to Back Flow Chart for Wide I/O
13. Assessment and Characterization of Stress Induced by Via-First TSV Technology
14. TSV and Cu-Cu direct bonding: two key technologies for High Density 3D
15. Process optimization and performance analysis of an electrostatically actuated varifocal liquid lens
16. Reliability study of 3D-WLP through silicon via with innovative polymer filling integration
17. Ultra low cost wafer level via filling and interconnection using conductive polymer
18. Process and RF modelling of TSV last approach for 3D RF interposer
19. Gold-tin bonding for 200mm wafer level hermetic MEMS packaging
20. Through Silicon Via technology using tungsten metallization
21. Investigation on TSV impact on 65nm CMOS devices and circuits
22. Effects of stress in polysilicon VIA - first TSV technology
23. Hermetic wafer-level packaging development for RF MEMS switch
24. Through Silicon Via polymer filling for 3D-WLP applications
25. TSV as an alternative to wire bonding for a wireless industrial product: another step towards 3D integration
26. Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs
27. Process solutions and polymer materials for 3D-WLP through silicon via filling
28. Development and characterisation of a 3D technology including TSV and Cu pillars for high frequency applications
29. Development and characterisation of high electrical performances TSV for 3D applications
30. Mid-process through silicon vias technology using tungsten metallization: Process optimazation and electrical results
31. Polymer filling of medium density through silicon via for 3D-packaging
32. 3D integration technology for set-top box application
33. New trends in wafer level packaging
34. Reliability characterization and process optimization of Ni-based microinsert interconnections for flip chip die on wafer attachment
35. Cost effective dry lithography solution for through silicon via technology
36. Integration of a temporary carrier in a TSV process flow
37. Low Cost Lithography Solution for Advanced Packaging and Application to Through Silicon Via Process
38. Enabling technologies for 3D integration: From packaging miniaturization to advanced stacked ICs
39. New routes and diversifications ofr nanoelectronics by the end of the roadmap and beyond
40. Facilitating Ultrathin Wafer Handling for TSV Processing
41. Through Silicon Vias Technology for CMOS Image Sensors Packaging: Presentation of Technology and Electrical Results
42. Wafer level packaging technology development for CMOS image sensors using Through Silicon Vias
43. Through silicon vias technology for CMOS image sensors packaging
44. Test structures for the evaluation of 3D chip interconnection schemes
45. Reliability Aspects of Microinsert Based Interconnection Technologies
46. High Aspect Ratio Vias First for Advanced Packaging
47. Wafer Level Thin Film Encapsulation for BAW RF MEMS
48. Detailed Characterisation of Ni Microinsert Technology For Flip Chip Die on Wafer Attachment
49. Via First Technology Development Based on High Aspect Ratio Trenches Filled with Doped Polysilicon
50. Silicon Through Vias for System-on-Wafer (SoW): Technology and SiO2 Insulation Layer Characterization
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