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This paper presents the open-source high-level synthesis (HLS) research framework Bambu. Bambu provides a research environment to experiment with new ideas across HLS, high-level verification and debugging, FPGA/ASIC design, design flow space exploration, and parallel hardware accelerator design. The tool accepts as input standard C/C++ specifications and compiler intermediate representations (IRs) coming from the well-known Clang/LLVM and GCC compilers. The broad spectrum and flexibility of input formats allow the electronic design automation (EDA) research community to explore and integrate new transformations and optimizations. The easily extendable modular framework already includes many optimizations and HLS benchmarks used to evaluate the QoR of the tool against existing approaches [1]. The integration with synthesis and verification backends (commercial and open-source) allows researchers to quickly test any new finding and easily obtain performance and resource usage metrics for a given application. Different FPGA devices are supported from several different vendors: AMD/Xilinx, Intel/Altera, Lattice Semiconductor, and NanoXplore. Finally, integration with the OpenRoad open-source end-to-end silicon compiler perfectly fits with the recent push towards open-source EDA.

In this talk, we review the current status of OpenROAD, which is an open-source end-to-end silicon compiler. The goal of OpenROAD is to reduce cost, expertise, schedule and risk barriers that face system designers today. The open-source flow builds around an industrial strength open-source design database, and incorporates a number of design tools that include physical synthesis synthesis, floorplanning, placement, clock tree synthesis, global routing and detailed routing. The flow also incorporates analysis and support tools for static timing analysis, parasitic extraction, power integrity analysis, and cloud deployment. The entire flow can be customized through scripting and enables users to experiment with various tool options and optimizations.

We describe the planned Alpha release of OpenROAD, an open-source end-to-end silicon compiler. OpenROAD will help realize the goal of "democratization of hardware design", by reducing cost, expertise, schedule and risk barriers that confront system designers today. The development of open-source, self-driving design tools is in and of itself a "moon shot" with numerous technical and cultural challenges. The open-source flow incorporates a compatible open-source set of tools that span logic synthesis, floorplanning, placement, clock tree synthesis, global routing and detailed routing. The flow also incorporates analysis and support tools for static timing analysis, parasitic extraction, power integrity analysis, and cloud deployment. We also note several observed challenges, or "lessons learned", with respect to development of open-source EDA tools and flows.

Engineering is the science of converting theory into practice. It is also the "art" of technical design. Among all engineering disciplines semiconductor electronic design has pushed the limits of true design automation far further than any other technical discipline. Armies of engineers were needed to design the Airbus A380, yet it is morphologically identical to a Boeing 747 designed using slide rulers 50 years ago. Contrast that to IC designers who build a billion-component chip from idea to hardware in just a few months. And they do that while the scale of the design reliably doubles every 2 years. Enabling this unprecedented degree of electronic design automation are a set of algorithms chained together as a flow that crosses several design abstractions down to a physical circuit mask pattern. During his illustrious career Ralph Otten's ideas and vision have shaped design automation in significant ways: by contributing algorithms and by defining methodologies to safely cross abstraction levels using automated tools. Ralph Otten's career parallels the development of circuit design flows from birth to mature flows. He developed the very first floorplan representations and worked on the very first logic synthesis flows (then called a "silicon compiler"). As director of education Ralph has set new directions, celebrating the strong points of the broader Electrical Engineering discipline. This presentation will address the the impact he has putting putting EDA on the map as an engineering discipline with a solid theoretical foundation. As a result, visionary-yet-small university projects matured into a coherent industrial-strength tools flows.

The continuous miniaturization and the increased complexity of today’s integrated circuits has led to a demand for faster simulation algorithms for photolithography, which is one of the most critical VLSI technology steps. Dedicated processors that execute an algorithm that simulates this process would be a valuable tool in the hands of the process engineer. A method for designing a dedicated processor, which executes a cellular automaton algorithm that simulates the photolithography process, using a genetic algorithm, is described in this paper. Starting from a cellular automaton with continuous state space which simulates the photolithography process, the genetic algorithm is used to find a cellular automaton with discrete state space, having the smallest possible lattice size and the smallest possible number of discrete states, the results of which are as close as possible to the results of the cellular automaton with continuous state space. The dedicated processor that executes the discrete cellular automaton algorithm was designed to the level of a silicon compiler output. The generality of the proposed design method is discussed.

This paper describes a new CAD tool, FTROM — Fault-Tolerant ROM compiler, which synthesizes layout geometries of fault-tolerant ROM modules with flexible, user-specified geometry and CMOS design-rule parameters. This physical design tool produces high-quality built-in self-testable (BIST) and fault-tolerant ROM layouts and uses a novel, minimum-delay overhead approach for fault-tolerance. A tool like FTROMeliminates the high cost of external testing of embedded ROM macros with I/O pins that are diƒcult to control and observe. ( 1998 Published by Elsevier Science B.V. All rights reserved.

The architectural design and VLSI implementation of a highly reconfigurable dataflow RISC (DF-RISC) processing element (PE) are presented. This processor forms an element of a processor array (DF-RISC-PA) which possesses the features of both static and dynamic dataflow models. The array can be programmed to execute arbitrary algorithms (recursive or irregular) in both static and dynamic manner. The processor array is modelled at the behavioural level in VHDL. The gate level implementation and VLSI layout of both the PE and the array are obtained with the help of OASIS Silicon compiler by translating the VHDL model to Logic3. Sample computations are mapped to illustrate functionality. The design is validated at all levels of abstraction. The results of simulation of the PE array are presented. The architecture is compared with previous approaches. The prototype PE requires 4261 CMOS gates and uses an area of 7512 × 8081 μm2.

One approach to the design of VLSI systems involves the use of asynchronous circuits that communicate by handshaking with each other. The control circuitry generated when following this approach often includes large trees of binary sequencer components. This paper demonstrates that there is scope here for optimization (in order to improve size, speed and energy consumption). Indeed, an industrial-strength silicon compiler has now been modified to take advantage of this fact. The problem that is addressed concerns the design of efficient control circuits that sequence N four-phase handshakes ( N > 2). Muller's speed-independent discipline facilitates the design of such circuits. SI-Algebra, a calculus that supports that discipline, is used to specify the problem and to verify (using recursion-induction) various implementations. Simple counting arguments at the gate level establish that optimization using these implementations is worthwhile.

Architecture design techniques for implementing both single-rate and multirate high throughput finite impulse response (FIR) digital filters are explored, with an emphasis on those which are applicable to automated integrated circuit layout techniques. Various parallel architectures are examined based on the criteria of achievable throughput versus hardware complexity. Well-known techniques for reduced complexity and computation time are briefly summarized, followed by the introduction of several new techniques which offer further gains in both throughput and circuitry reduction. An architecture for mirror-symmetric polyphase filter banks is derived which exploits the coefficient symmetry between multiple filters to reduce hardware. Finally, the evolution of a silicon compiler which utilizes all of these techniques is presented, and results are given for compiled filters along with comparisons to other compiled and custom FIR filter chips.

In this paper, a silicon compiler for analog fuzzy controllers is described. The layout is generated automatically, starting from global-system specifications accepted as a set of classical fuzzy rules involving fuzzy sets as well as numerical data, often available from numerical examples. The system relies on a library of basic cells designed using a CMOS n-well 0.7 /spl mu/m technology and on the use of Cadence software. Multi-inputs multi-outputs fuzzy logic-based controllers are synthesized, and the area and power requirements by any specific application are optimized. Some prototypes designed using the proposed methodology have been fabricated. For example, a two-inputs two-outputs fuzzy controller implementing a 2D rational function and a sinusoidal function requires, including the I/O circuitry, 1.9 mm/sup 2/ of silicon area, and the total power consumption is 44 mW at 5 V power supply. The maximum propagation delay, assuming a step input function, is 0.57 /spl mu/sec. The total computation time using a SUN Sparc2 Workstation is about 25 min, from specification of the expected behavior to layout.

The design of graphics ASICs for geometry and rasterisation processing has traditionally involved the use of schematic design entry whereby functional blocks are netlisted and instantiated on the schematic. This methodology is fine at the top most hierarchical levels of a design but becomes tedious and error prone at the lower gate levels. Often these designs are targeted at custom ASICs through the use of silicon compiler technology. Unfortunately, this is an expensive and risky approach to implementing these ASICs, particularly for University research laboratories where additional funding may not be available to cover non-recurring engineering costs, such as multiple mask runs, which may be needed due to design errors. This paper presents an alternative to these traditional approaches. A new approach, top down ASIC design with logic synthesis and optimisation targeting FPGA ASICs, is presented. Furthermore, exciting new reconfigurable FPGA, FPIC, and MCM technologies are now becoming available at a fraction of the cost of ASIC fabrication. These are ideal for prototyping, and we can reuse this technology for many new graphics hardware designs. We demonstrate through some examples of our graphics rasterisation hardware the benefits of this new approach.

The CATHEDRAL Silicon Compilers synthesize hardware for DSP algorithms specified in Silage, a high level applicative language. In order to optimize the results of the silicon compilation in terms of chip-area and/or throughput, the user often massages the specification applying transformations to the Silage code. To guarantee that the transformations preserve the behavior of the specified algorithm, the formal semantics of the specification language had to be defined. The semantics has been used to prove in HOL the correctness of the transformations and to prove properties of the specification. We are currently building a system where a menu of useful andcorrectness preserving transformations will be available to the user. In this system the user could choose appropriate transformations from the menu taking advantage of his creativity and expertise to interactively guide the silicon compiler, without the risk of introducing inconsistencies. This article describes the formalmulti-rate semantics of a substantial subset of Silage and illustrates some formally verified transformations.

This paper presents a new, silicon compiler‐based methodology for designing application‐specific chips. A newly developed behavioral silicon compiler called DSS is used to implement standard DSP components. This compiler includes a design specification language parser, a high‐level synthesizer and a parameterized module generator. The goal is to reduce the overall design time of DSP systems by offering the designer a complete compilation environment. Design space exploration is illustrated in examples, to show the ability of a silicon compiler to create and test many design alternatives in a very short time period. Designers using this compiler are encouraged to try several designs until a feasible one is found. Design examples are given in later sections to illustrate the synthesis result.

A greedy optimization technique for minimizing the area of linear digital systems using a combination of common subexpression elimination and modification of multiplier coefficients is proposed. Since the amount of logic required by a coefficient multiplier is dependent on the value of the coefficient, the given system is transformed, using splitting of coefficients, in such a way that the overall circuit requires a smaller area. The approach explores a much larger design space as compared to previously known techniques. The approach is the first to optimize numerically intensive digital circuits by additive decomposition of multiplier coefficients. The new synthesis scheme generates functionally equivalent but structurally different circuits with a 15 to 40% reduction in area over conventional methods, for practical circuits with DSP applications. >

A parameterised microcontroller for use in compiled single-chip systems is described. Key processor parameters may be varied over a wide range (minimum data bus width is 4 bits) in order to optimise chip area and performance for a given application. The instruction set is uniform and compact, does not vary when the microcontroller design is scaled, and produces dense code. A working prototype has been produced in Mietec 2.4 mu CMOS using the Cathedral silicon compiler, and a variety of 1.2 mu and 0.7 mu layouts generated from parameterised netlists in the Hilarics and VHDL languages, using both the Cathedral and Synopsys compilers. Code density and layout results are given.

The paper describes the implementation of a bit-serial systolic array architecture for a multilayer perceptron. It is shown that both the recall phase and learning phase can be mapped onto a similar systolic array structure, with minor differences. As a result, a combined systolic array structure is proposed for both the recall phase and the learning phase. The design is simulated using the FIRST silicon compiler to solve the exclusive OR problem, and then compared with a 32-bit floating-point simulation. The central element, multiply-and-accumulate operator was fabricated using a 1.2 μm double metal CMOS p-well process by ORBIT semiconductor, and found to perform satisfactorily. The required chips were implemented with the same technology, and performance parameters estimated. Furthermore, the performance of this architecture in solving the NETtalk problem is compared with other implementations.

The design of a controller circuit for an Amharic numerical display is described. The Amharic numerals, comprising numerals from 0 to 19, are displayed on two 5*7 dot or light-emitting-diode matrixes. The circuit controls the state (i.e. on or off) of each dot to display the desired Amharic numerals. The design is compiled in an integrated circuit chip form using a silicon compiler tool. Prototypes were manufactured and tested. The possible insertion of the design in a TV display control system is discussed. >

An integrated software system that facilitates the design, and integrated-circuit layout of continuous-time OTA-C filter biaquad-based structures with typical cutoff frequenceis for a 3µmtechnology in the 500 kHz-8 MHz range is described. The proposed integrated software system consists of three separate software modules written in the C language for the Apollo workstation (DN3000). The first module is a general filter approximation package. This program can approximate conventional magnitude, arbitrary magnitude, arbitrary group delay equalizer, arbitrary magnitude with group delay specifications. The second module aides in the synthesis of the biquad-based OTA-C filter structures. This module is unique in that the C code has the rule-based language CLIPS embedded within the code, and takes into account OTA-C filter nonidealities. An expert system using CLIPS was developed to select an appropriate OTA-C filter structure based on the nonidealities of the structures. After the filter structure has been chosen, the program will guide the user in the calculation of the capacitor values. These calculations are based on the nonidealities of the OTAs included in the standard cell library for layout, in addition the design of special purpose OTA as another alternative is also considered. Furthermore, the program will develop the necessary input files for the layout generator. The final module is a modified version of AIDE2, a standard cell layout generator for switched-capacitor circuits. The input files to the modified AIDE2 is a C language program that describes the circuit (i.e., standard cells and their netlist). The output file is a CALTECH Intermediate Format (CIF) file that is required for fabrication.

This article presents a discrete cosine transform (DCT) processor for high definition television (HDTV) by using an extended version of DSP Silicon Compiler. The extension is mainly concerned with module generation functions. A matrix-vector product module composed of multiply-accumulators (MACs) is newly added to the silicon compiler. The compiler accomplishes placement of leaf-cells and routing between the cells, referring to a prototype layout for the MAC. The prototype, which consists of a Booth multiplier and a carry look ahead adder, is carefully designed to attain high operation speed. The processor developed by the silicon compiler carries out 8×8 DCT and its inverse transform (IDCT). In order to evaluate the newly extended functions in the compiler, the architecture employed for the processor is based on the matrix-vector product method. By using DSP Silicon Compiler and 0.8 µm triple metal CMOS technology, the DCT processor is easily implemented with error-free environment and achieves a 50MHz data rate, which meets Japanese HDTV base line signal processing. The chip is implemented on a 12.80×12.57mm2 area.

Faced with the challenge of designing correct circuits, the research community has been applying alternative verification methodologies istead of only traditional methods like ad hoc simulation. The best choice among alternatives like tautology checking, symbolic simulation, and theorem proving depends very theorem proving is best applicable, one is faced with the problem of choosing a formalism. This article compares the proof assistant HOL and the theorem-prover Boyer-Moore based on a practical experience with both systems in order to verify a combinatorial and parameterized hardware module from the CATHEDRAL II Silicon Compiler library. Although the comparison is based on a specific application, the general features, advantages, and drawbacks of both systems are discussed, with consideration given to the verification of other kinds of circuits.

We present the design of a Sinc Cubed Decimator and of a Front End DSP Engine for Analog to Digital Conversion using high-level synthesis. The input language was SystemC and the High Level Synthesis tool was Cadence's C to Silicon compiler. Area and timing results, as well as comments on the overall experience, are also presented.

This paper presents the possibilities offered by ASA's Topology Description Language and Compactor tool for creating technology-independent module generators. It will be shown that the actual layout work has to be done only once for a symbolic library which can be compacted to various technologies. The compacted results are comparable in density and performance to handcrafted layouts; furthermore the design time for implementing new technologies is substantially shortened.

We describe the MIM2SOLO Silicon Compiler which integrates the MIMOLA high-level synthesis system and the SOLO 1400 standard-cell IC design system. Key features of the system are synthesis from an algorithmic description, full simulation support with automatic test pattern generation, and support of hybrid (analogue/digital) designs. We present a CISC processor designed both traditionally and using MIM2SOLO and compare design efforts and layout. As an example of hybrid designs, we discuss a digital filter with on-chip analogue-digital and digital-analogue converters.

Transform techniques are becoming more and more important in digital signal processing, with particular reference to coding problems, owing to their capability of redundancy reduction by signal decorrelation. The MMT (Matrix Multiplier Transform) is a high speed device able to perform any type of two-dimensional separable unitary transform. It is realized with 1.5 μm technology and can work at operating frequencies up to 16.75 MHz, and so is able to work on TV signal in real time. An analysis of the truncation errors due to the use of a finite arithmetic and their propagation has been performed. That analysis, together with the decision to make use of a silicon compiler in the design stage, made it possible to maintain a parametrical architecture so that MMT can be easily adapted to many applications.

VLSI chips for luminance/chrominance (Y/C) signal separation and synthesis have been developed. Application-specific FIR filter structures and canonical signed-digit representation (CSR) multipliers used in the filters make it possible to develop compact high-speed VLSI chips. A silicon compiler, which employs the optimal FIR filter structures and supplies the optimal filter design faculty, has contributed to quick VLSI development. Y/C signal separation using four video FIR filters and Y/C signal synthesis using three video FIR filters are implemented on single chips by 1.2- mu m CMOS technology. >

QUISC3 is a distributed processing silicon compiler, operating under the ELECTRIC Layout Tool. This new version of QUISC is designed to perform distributed processing on a LAN of workstations. It exploits the inherent hierarchy of VHDL to create macrocells on remote network servers, thereby improving both user response time and the allowable design size.

The design and implementation of a compiler for two very high level languages are addressed. The first language is a set language similar to VERS and SETL. The second language is a novel signal processing language. The compiler uses data flow and type information to constrain possible choices before choosing a possible implementation. Heuristic search is then used to choose from competing concrete implementations of abstract data types. Constraint propagation is used at every selection step to remove incompatible configurations from the search, thereby reducing the search space considerably. A microprogram control store is automatically generated. The output of the compiler is a parts list, a net list of module interconnections, and the fields of the control store. >

Complex DSP (digital signal processor) ASICs (application-specific integrated circuits) typically feature high-quality filters implemented as dedicated blocks. FIDYS (filter 1di synthesis system) is a new VLSI recursive filter compiler, specifically designed to meet those needs. It is fully integrated from behavioral frequency template specifications down to layout. It comprises a specific approximation and synthesis procedure, the generation of a systolic architecture with parameterized pipelining based on dedicated bit-serial operators, and final generation of a densely packed layout based on a minimal dedicated set of 1- mu m CMOS basic cells. A lossless discrete integrator ladder filter structure is used. It features an outstanding low sensitivity and a high degree of modularity and regularity that directly result in streamlined hardware and an efficient placement with minimal routing overhead. Examples of representative applications for telecommunications circuits are presented. >

A novel design methodology for rapid implementation of cheap high-performance ASICs (application-specific integrated circuits) is introduced. The method derives from high-level algorithm specifications or from high-level source programs not only the target hardware, but (in contrast to silicon compilers) also the machine code to run it. The method is based on a novel sequential machine paradigm where execution is used (being orders of magnitude more efficient) instead of simulation and where programmers may do the design job, rather than real hardware designers. It is shown that, for a very large class of commercially important algorithms (DSP, graphics, image processing and many others), this paradigm is orders of magnitude more efficient that the von Neumann paradigm. Compared to von-Neumann-based implementations, acceleration factors of up to more than 2000 have been obtained experimentally. The performance of ASICs obtained by this methodology is mostly competitive with ASIC designs obtained in the much slower and much more expensive traditional way. As a by-product the new methodology also supports the automatic generation of universal accelerators for coprocessor use in workstations. >

A VLSI coprocessor that radically improves the real-time performance of the Ada tasking model, especially the rendezvous, is discussed. An overview of multilevel design is given, and design levels and models are examined. A description is given of the design strategy, which entails stepwise refinement of functional models representing the coprocessor at more and more detailed levels. A chip was generated using the Genesil silicon compiler, but most of the design was defined and verified on the instruction-set-processor and register-transfer levels. >

Performance of relational database systems is a major impediment to their use in many applications. We have designed and implemented a customized RISC processor to accelerate associative search and aggregation operations for relational database systems. Since the processor is programmable and supports many queries concurrently, a system utilizing tens of such processors is capable of handling thousands of complex search requests simultaneously. While the design of a VLSI programmable processor is a complex process, research prototyping requires a fast turnaround design process. We took advantage of the logic programming paradigm and the silicon compiler technology to explore and simulate architecture alternatives prior to the actual implementation. The prototyping process allowed us to complete the chip design in nine months. The resulting processor, fabricated in 2 Itm CMOS technology, consists of 91,000 transistors, executes over 18 million predicate evaluations per second, and searches database contents at 74 megabytes per second.

A priority interrupt controller and synchronizer for a MC68008 microprocessor have been designed with the help of the VHDL language, a silicon compiler and a standard cell library. IEEE Standard 1076 VHSIC Hardware Description Language defines this language as a tool for structural and behavioural specification for very high speed integrated circuits. VHDL supports a wide range of design abstractions. The paper examines the procedures and the use of hardware and software tools in the design and simulation of the circuit.

An architecture is presented for hard-wired data-flow algorithms which is based on the transmission of arithmetic data one digit at a time serially, and performance of operations digit-serially on that data. It is shown that digit-serial computation gives rise to particularly efficient chip designs, and that choice of digit-size allows the user to match throughput requirements to specifications. Details of the implementation of the individual operators as a cell-library of silicon CMOS circuits are given and mention is made of the software environment (silicon compiler) which allows the rapid translation of algorithms to integrated circuits. >

A testability strategy for a complex VLSI device that is implemented in the Piramid digital-signal-processor silicon compiler is presented. The macro test method proposed supports built-in self-test, scan test, restricted partial scan, and test-control logic at various levels in the design hierarchy. The strategy uses techniques such as a macro test plan, transfer information, and intermediate vector storage. The overhead from adding testability is only 10% of the total area and test-program generation is done with 100% fault coverage in a very short time, since there is no need for global test-pattern generation. A set of tools that guide the testability implementation from design to the final test program is described. >

A computer program for microcode compilation for custom digital signal processors is presented. This tool is part of the CATHEDRAL II silicon compiler. The following optimization problems are highlighted: scheduling, hardware assignment, and loop folding. Efficient techniques to solve these problems are developed. This allows for the automatic synthesis of processor architectures which simultaneously exploit pipelining and parallelism. A demonstrator design is presented. >

Traditional scan design techniques such as level-sensitive scan design, scan path, and random-access scan suffer from the drawback that the extra test application effort (which includes both time and memory) required is directly proportional to the number of latches and can become quite significant. A scan design technique termed partial parallel scan which reduces test application effort by one to two orders of magnitude is presented. Theoretical and practical aspects of the design method are discussed. The practical use of the partial parallel scan technique has been demonstrated with an LSI circuit and a VLSI circuit designed using silicon compiler tools. >

Static random access memory (SRAM) compiler is the silicon compiler that generates SRAM IP cores with various specifications. A high performance and flexible SRAM compiler is proposed in this paper. Our compiler uses block assembly techniques with uniform physical data syntax. This encapsulates the compiler from low level module information. Hence it is self-adaptive to the migration of technology nodes. Our experiment result shows that this compiler can generate a wide capacity range of SRAM with relatively high performance.

This document describes briefly projects which use the HOL proof system, based on contributions from the user community. The entries are in somewhat haphazard order and classification; the intent is to provide 0 brief synopsis of applications and a directory for future contacts. This list is by no means comprehensive - it just contains the contributions I have received.

A 43-tap half-band FIR digital filter generated by a silicon compiler in 1.2-pm CMOS is described. The multiplierless fixed-coefficient filter has a folded transpose direct-form structure, uses carry-save addition, pipelining, and a true single-phase clocking scheme. The 6.5 x 6.3-mm2, 66,000 transistor chip has been verified at 150 MHz with a power dissipation of 2.0 W.