405 results on '"Sigl, Georg"'
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2. Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track
3. The Impact of Hash Primitives and Communication Overhead for Hardware-Accelerated SPHINCS+
4. A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts
5. The Impact of Hash Primitives and Communication Overhead for Hardware-Accelerated SPHINCS+
6. The Cost of OSCORE and EDHOC for Constrained Devices
7. Secure and User-Friendly Over-the-Air Firmware Distribution in a Portable Faraday Cage
8. TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix)
9. Protecting RESTful IoT Devices from Battery Exhaustion DoS Attacks
10. Network Scanning and Mapping for IIoT Edge Node Device Security
11. A Secure Dual-MCU Architecture for Robust Communication of IIoT Devices
12. Efficient Intrusion Detection on Low-Performance Industrial IoT Edge Node Devices
13. EyeSec: A Retrofittable Augmented Reality Tool for Troubleshooting Wireless Sensor Networks in the Field
14. Sensors for Data Bus Protection
15. Tamper-Sensitive Design of PUF-Based Security Enclosures
16. A Power Side-Channel Attack on the Reed-Muller Reed-Solomon Version of the HQC Cryptosystem
17. A Second Look at the ASCAD Databases
18. Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoC
19. A Power Side-Channel Attack on the CCA2-Secure HQC KEM
20. DOMREP II
21. Fault-Simulation-Based Flip-Flop Classification for Reverse Engineering
22. Post-Quantum Signatures on RISC-V with Hardware Acceleration
23. A Second Look at the ASCAD Databases
24. A Power Side-Channel Attack on the Reed-Muller Reed-Solomon Version of the HQC Cryptosystem
25. HW-Acceleration for Edge-AI
26. On Error Correction for Physical Unclonable Functions
27. Pushing the Limits Further: Sub-Atomic AES
28. Machine learning and structural characteristics for reverse engineering
29. Error Correction for Physical Unclonable Functions Using Generalized Concatenated Codes
30. Side-Channel Analysis and Countermeasures for Physical Unclonable Functions
31. Remote Security Threats and Protection of Modern FPGA-SoC Architectures
32. Secure Lightweight Authenticated Encryption for Critical Infrastructures in the Internet of Things
33. Secure and User-Friendly Setup and Maintenance of Wirelessly Interconnected Embedded Systems
34. Malware Detection and Countermeasures for Constrained Internet of Things Devices
35. Towards Secure Coprocessors and Instruction Set Extensions for Acceleration of Post-Quantum Cryptography
36. High-Resolution EM Attacks Against Leakage-Resilient PRFs Explained : And an Improved Construction
37. A Power Side-Channel Attack on the CCA2-Secure HQC KEM
38. How to Break Secure Boot on FPGA SoCs Through Malicious Hardware
39. Squeezing Polynomial Masking in Tower Fields : A Higher-Order Masked AES S-Box
40. Automated Detection of Instruction Cache Leaks in Modular Exponentiation Software
41. Towards Side-Channel Secure Firmware Updates : A Minimalist Anomaly Detection Approach
42. Uniform instruction set extensions for multiplications in contemporary and post-quantum cryptography
43. Towards Efficient Evaluation of a Time-Driven Cache Attack on Modern Processors
44. Precise Laser Fault Injections into 90 nm and 45 nm SRAM-cells
45. seTPM: Towards Flexible Trusted Computing on Mobile Devices Based on GlobalPlatform Secure Elements
46. Low-latency X25519 hardware implementation: breaking the 100 microseconds barrier
47. Fast and reliable PUF response evaluation from unsettled bistable rings
48. Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection
49. Efficient security zones implementation through hierarchical group key management at NoC-based MPSoCs
50. Towards Protected MPSoC Communication for Information Protection against a Malicious NoC
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