Search

Your search keyword '"Sicard, Gilles"' showing total 351 results
Start Over Author "Sicard, Gilles"

Refine your results

more »

more »

more »

more »
351 results on '"Sicard, Gilles"'

2. From Near-Sensor to In-Sensor: A State-of-the-Art Review of Embedded AI Vision Systems.

Author

Fabre, William, Haroun, Karim, Lorrain, Vincent, Lepecq, Maria, and Sicard, Gilles

Subjects
COMPUTER vision, ARTIFICIAL intelligence, CONVOLUTIONAL neural networks, FEATURE extraction, IMAGE sensors, LOW vision
Abstract

In modern cyber-physical systems, the integration of AI into vision pipelines is now a standard practice for applications ranging from autonomous vehicles to mobile devices. Traditional AI integration often relies on cloud-based processing, which faces challenges such as data access bottlenecks, increased latency, and high power consumption. This article reviews embedded AI vision systems, examining the diverse landscape of near-sensor and in-sensor processing architectures that incorporate convolutional neural networks. We begin with a comprehensive analysis of the critical characteristics and metrics that define the performance of AI-integrated vision systems. These include sensor resolution, frame rate, data bandwidth, computational throughput, latency, power efficiency, and overall system scalability. Understanding these metrics provides a foundation for evaluating how different embedded processing architectures impact the entire vision pipeline, from image capture to AI inference. Our analysis delves into near-sensor systems that leverage dedicated hardware accelerators and commercially available components to efficiently process data close to their source, minimizing data transfer overhead and latency. These systems offer a balance between flexibility and performance, allowing for real-time processing in constrained environments. In addition, we explore in-sensor processing solutions that integrate computational capabilities directly into the sensor. This approach addresses the rigorous demand constraints of embedded applications by significantly reducing data movement and power consumption while also enabling in-sensor feature extraction, pre-processing, and CNN inference. By comparing these approaches, we identify trade-offs related to flexibility, power consumption, and computational performance. Ultimately, this article provides insights into the evolving landscape of embedded AI vision systems and suggests new research directions for the development of next-generation machine vision systems. [ABSTRACT FROM AUTHOR]

Published
2024
Full Text
View/download PDF

4. Low-Throughput Event-Based Image Sensors and Processing

Author

Fesquet, Laurent, Tran, Rosalie, Lesage, Xavier, Akrarai, Mohamed, Mancini, Stéphane, Sicard, Gilles, Circuits, Devices and System Integration (TIMA-CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), and IEEE

Subjects
time to first spike pixel, event-based image processing, event-based image sensor, low power, PACS 85.42, dynamic vision sensor, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, asynchronous circuit
Abstract

International audience; This paper presents new kinds of image sensors based on TFS (Time to First Spike) pixels and DVS (Dynamic Vision Sensor) pixels, which take advantage of non-uniform sampling and redundancy suppression to reduce the data throughput. The DVS pixels only detect a luminance variation, while TFS pixels quantized luminance by measuring the required time to cross a threshold. Such image sensors output requests through an Address Event Representation (AER), which helps to reduce the data stream The resulting event bitstream is composed by time, position, polarity, and magnitude information. Such a bitstream offers new possibilities for image processing such as event-by-event object tracking. In particular, we propose some processing to cluster events, filter noise and extract other useful features, such as a velocity estimation.

Published
2023

13. O

Author

Veasey, Sigrid C., Becker, Wolfgang, Scudder, Charles, Pyrski, Martina, Zufall, Frank, Brennan, Peter, Giurfa, Martin, Mouret, Aurelie, Coureaud, Gérard, Datiche, Frédérique, Briand, Loïc, Lazarini, Françoise, Cloutier, Jean-François, Hays, Nicholas P., Lledo, Pierre-Marie, Sassoè-Pognetto, Marco, Sicard, Gilles, Fontanini, Alfredo, Stevenson, Richard J., Kay, Leslie M., Grubb, Matthew S., Albrecht, J, Wiesmann, M, Slotnick, Burton, Weiler, Elke, Wilson, Donald A., Bell, Heather, Chen, Chien-Fu, Sandoz, J. C., Hatt, Hanns, Kaneko, Chris R. S., Brembs, Björn, Lappe, Markus, Scudder, Charles A., Ravel, Nadine, Gervais, Rémi, Chapuis, Julie, Martin, Claire, Binder, Marc D., editor, Hirokawa, Nobutaka, editor, and Windhorst, Uwe, editor

Published
2009
Full Text
View/download PDF

15. Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits

Author

Bouesse, Fraidy, Sicard, Gilles, Renaudin, Marc, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Goubin, Louis, editor, and Matsui, Mitsuru, editor

Published
2006
Full Text
View/download PDF

20. TAST Profiler and Low Energy Asynchronous Design Methodology

Author

Slimani, Kamel, Rémond, Yann, Sicard, Gilles, Renaudin, Marc, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Macii, Enrico, editor, Paliouras, Vassilis, editor, and Koufopavlou, Odysseas, editor

Published
2004
Full Text
View/download PDF

23. Low-Power Asynchronous A/D Conversion

Author

Allier, Emmanuel, Fesquet, Laurent, Renaudin, Marc, Sicard, Gilles, Goos, Gerhard, editor, Hartmanis, Juris, editor, van Leeuwen, Jan, editor, Hochet, Bertrand, editor, Acosta, Antonio J., editor, and Bellido, Manuel J., editor

Published
2002
Full Text
View/download PDF

26. A hybrid event-based pixel for low-power image Sensing

Author

Akrarai, Mohamed, Margotat, Nils, Sicard, Gilles, Fesquet, Laurent, Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), European Project: 783127,H2020-EU.2.1.1.7. - ECSEL,OCEAN12(2018), and Circuits, Devices and System Integration (TIMA-CDSI)

Subjects
time to first spike pixel, event based techniques, dynamic vision sensor pixel, PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; This article presents a hybrid pixel dedicated to event-based image sensors, which suppresses spatial and temporal redundancies. This pixel is a combination between two kinds of pixels, known as TFS and DVS. The first one is able to reduce - associated to a dedicated readout - spatial redundancies, while the second manages the temporal redundancies. Each pixel is classically built with a photodiode but this hybrid structure shares the photodiode between the DVS and the TFS pixels. In our design, 4 TFS pixel photodiodes are shared with 1 DVS pixel, which exploits the average current of the latter. In order to evaluate such a pixel, a comparison is made between a hybrid pixel matrix and a matrix composed of TFS and DVS pixels.The evaluation is made in terms of activity and power but also by analyzing their fill-factor, circuitry and layout. A testchip including the 2 event-based image sensors has been designed in FDSOI 28 nm technology from STMicroelecronics.

Published
2021

35. Récupération des capacités olfactives : un entraînement particulier est possible chez les professionnels du vin !

Author

Tempere, Sophie, de Revel, Gilles, Sicard, Gilles, Unité de Recherche Oenologie [Villenave d'Ornon], Université de Bordeaux (UB)-Institut des Sciences de la Vigne et du Vin (ISVV)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), and Admin, Oskar

Subjects
[SDV.BV]Life Sciences [q-bio]/Vegetal Biology, [SDV.BV] Life Sciences [q-bio]/Vegetal Biology, ComputingMilieux_MISCELLANEOUS
Abstract

Article dans une revue professionnelle

Published
2020

36. Récupération des capacités olfactives : quel entrainement après la COVID-19

Author

Tempere, Sophie, De Revel, Gilles, Sicard, Gilles, DESAILLY, Marion, Unité de Recherche Oenologie [Villenave d'Ornon], Université de Bordeaux (UB)-Institut des Sciences de la Vigne et du Vin (ISVV)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), and Centre National de la Recherche Scientifique (CNRS)

Subjects
[SDE] Environmental Sciences, [SDV] Life Sciences [q-bio], [SDV]Life Sciences [q-bio], Oenologie, [SDE]Environmental Sciences, Covid-19, Odorat
Published
2020

47. Exploring Hierarchical Machine Learning for Hardware-Limited Multi-Class Inference on Compressed Measurements

Author

Benjilali, Wissam, Guicquero, William, Jacques, Laurent, Sicard, Gilles, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), and UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique

Subjects
Computational complexity theory, Computer science, business.industry, SVM, 020208 electrical & electronic engineering, Decision tree, Cognitive neuroscience of visual object recognition, compressive sensing, Inference, 02 engineering and technology, Hierarchical clustering, Hierarchical classifier, Support vector machine, ComputingMethodologies_PATTERNRECOGNITION, 0202 electrical engineering, electronic engineering, information engineering, embedded multi-class inference, 020201 artificial intelligence & image processing, Hierarchical learning, Cluster analysis, business, Classifier (UML), Computer hardware, clustering
Abstract

This paper explores hierarchical clustering methods to learn a hierarchical multi-class classifier on compressed measurements in the context of highly constrained hardware (e.g., always-on ultra low power vision systems). In contrast to the popular multi-class classification approaches based on multiple binary classifiers (i.e., one-vs.-all and one-vs.one [1]), a hierarchical classifier requires only O(log 2 C) binary classifiers in a decision tree. In this work, we investigate three clustering methods used to construct balanced clusters at each node thus reducing the depth of the decision tree in order to lower hardware requirements to its minimum. A binary Support Vector Machine (SVM) [2] classifier is then learned on Compressive Sensing measurements [3] at each node of the hierarchical tree. Our results, based on two object recognition databases (AT&T and COIL-100 databases), show the competitiveness of hierarchical classification in terms of hardware requirements (lower memory and computational complexity) as well as its classification accuracy.

Published
2019

48. An Analog-to-Information VGA Image Sensor Architecture for Support Vector Machine on Compressive Measurements

Author

Benjilali, Wissam, Guicquero, William, Jacques, Laurent, Sicard, Gilles, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), and UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique

Subjects
Video Graphics Array, Computer science, business.industry, Dimensionality reduction, SVM, 020208 electrical & electronic engineering, embedded object regognition, compressive sensing, Analog-to-digital converter, 02 engineering and technology, Facial recognition system, law.invention, Support vector machine, pseudo-random permutation, Compressed sensing, law, 0202 electrical engineering, electronic engineering, information engineering, Affine transformation, Image sensor, business, Computer hardware, Digital signal processing, Sigma-Delta
Abstract

This work presents a compact VGA (480 × 640) CMOS Image Sensor (CIS) architecture with dedicated end-of-column Compressive Sensing (CS) scheme allowing embedded object recognition. The architecture takes advantage of a low-footprint pseudo-random data mixing circuit and a first order incremental Sigma-Delta (ΣΔ) Analog to Digital Converter (ADC) to extract compressed features. The proposed CIS achieves an object recognition accuracy of ≃ 93% on the Georgia Tech face recognition database (GIT, 10 classes out of 50) thanks to a linear Support Vector Machine (SVM) classifier implemented by an optimized Digital Signal Processing (DSP). We stress that the signal independent dimensionality reduction performed by our dedicated CS scheme (1/480) allows to dramatically reduce memory requirements (≈ 32 kbit) related −in our case− to the ex-situ learned affine function of the linear SVM.

Published
2019

Catalog

Books, media, physical & digital resources
See catalog results