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A variety of resistive memories have been proposed in recent years. Among these emerging technologies, phase change memory (PCM) has received the most research attentions since it has the advantages of high scalability, non-volatility, fast access, strong data retention, low cost, and low power consumption. It is also considered as the most promising alternative of DRAM. In order to conquer the inevitable endurance problem of PCM cells which causes serious reliability and yield threats, hard repair and ECC (Error correction code) techniques are widely adopted. However, since soft errors are not a main threat for PCM, incorporating ECC for each data word is not a cost-effective technique since a lot of memory space is required for storing the check bits. In this paper, the progressive ECC techniques including the local progressive ECC (LPE) technique and the global progressive ECC (GPE) technique are proposed to solve this dilemma. The key innovation is to equip ECC for a data word when its first faulty cell is detected. In other words, we only equip fault detection code for data words such that the original code rate can be increased significantly. An ECC DRAM and an ECC CAM are used for storing check bits and accessing purposes, respectively. Hardware architectures for implementing the proposed GPE and LPE techniques are also provided. A simulator is developed for evaluating repair rate, reliability, yield, and hardware overhead. According to experimental results, the degradation of repair rate and reliability are almost negligible. However, the hardware overhead is at least 80% lower than the original ECC technique while maintaining the original reliability and yield levels.

In this article, we propose two kinds of electrical interconnect test methods for production tests and field ones of assembled circuit boards, which are performed prior to and after shipping to market, respectively. For these tests, we also propose a built-in test circuit. The methods we followed are based on the oscillation frequency of a relaxation oscillator (ROsc) embedded in integrated circuits (ICs). The frequency is measured as the number of pulse signals within a specified test time. Using the test methods, open defects at the interconnects between IC pins and a printed circuit board (PCB) are detected that are modeled as a resistor, a capacitor, and an open-circuit fault. We examined the detectability of open defects using the process variations afforded by SPICE simulation. The simulation results show that open defects were detected, modeled as a resistor of 45.8 $\Omega $ or above, along with open defects modeled as a capacitor and an open-circuit fault using the production test method. In addition, a resistance increase of 1.2 $\Omega $ at defect-free interconnects occurred after shipping to market was detected using the field test method. We also prototyped ICs with embedded ROscs and built an experimental circuit made of the ICs on PCBs. Moreover, we experimentally examined whether open defects could be detected. The results show that with the production test method, open defects modeled as a resistor of 10 $\Omega $ or above and modeled as a capacitor and an open-circuit fault can be detected.