Search

Your search keyword '"Shylashree, N."' showing total 47 results
Start Over Author "Shylashree, N."
47 results on '"Shylashree, N."'

3. Design of clock control block for DFT

Author

Shylashree N, Satish Tunga, Shaik Mahammad Ameer Afridi, and Sridhar V

Subjects
Design for testability, Clock control, Test data register, Launch on capture, Launch on shift, Dynamic power, Electrical engineering. Electronics. Nuclear engineering, TK1-9971
Abstract

DFT is a technique that converts the design into testable after manufacturing. As technology is shrinking, the complexity of inserting the DFT is becoming high. When it comes to DFT timing, controlling clocks in test mode is become a challenge nowadays. To achieve the high scan shift speed and to reduce the tester time, a new architecture is proposed in this work. The objective of this work is to propose a new design for clock controlling in DFT timing and working of the proposed block by configuring the different Test Data Registers. The proposed clock provides the clock intercepts for scan and debug modes along with features such as a single clock entry point per tile, clock stop using TDR, capture clock path same as functional mode path, and staggering pulse generation for LOS and LOC. The scannable logic in any tile must receive a clock from the clock control block. The tile level clock can be gated inside this block. A pulse generation logic is used to control the Gater inside the proposed design. The dynamic power consumption of the proposed architecture is compared with different clock architectures. The dynamic Power consumption is calculated as 60 mW which is less compared to already existing on-chip clock controllers in the DFT.

Published
2024
Full Text
View/download PDF

4. Multiscale Decomposition of HDR Images Using the Edge-Preserving Filters

Author

Anand Swamy, A. S., Shylashree, N., Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Nath, Vijay, editor, and Mandal, Jyotsna Kumar, editor

Published
2023
Full Text
View/download PDF

5. Image Sensor—CCD and CMOS

Author

Tejas, R., Macherla, Pavan, Shylashree, N., Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Nath, Vijay, editor, and Mandal, Jyotsna Kumar, editor

Published
2023
Full Text
View/download PDF

10. Design and Implementation of a Small Hand Held Camera Detector on FPGA

Author

Shylashree, N., Supritha, H. M., Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Nath, Vijay, editor, and Mandal, J. K., editor

Published
2021
Full Text
View/download PDF

11. Electrical Characterization of Sb2Se3 for Memory Applications

Author

Shylashree, N., Thonse, Adithya, Madhavan, Aditya, Sangeetha, B. G., Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Nath, Vijay, editor, and Mandal, J. K., editor

Published
2021
Full Text
View/download PDF

12. Structural Testing of Multichip Module SoC Components

Author

Hosur, Amruta, Shylashree, N., Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Liang, Qilian, Series Editor, Martin, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Nath, Vijay, editor, and Mandal, Jyotsna Kumar, editor

Published
2019
Full Text
View/download PDF

13. Design of Ternary SRAM Cell Based on Level Shift Ternary Inverter

Author

Shylashree, N., Hosur, Amruta, Praveena, N., Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Liang, Qilian, Series Editor, Martin, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Sridhar, V., editor, Padma, M.C., editor, and Rao, K.A. Radhakrishna, editor

Published
2019
Full Text
View/download PDF

16. Lossless HDR Image Compression by Modulo Encoding.

Author

Anand Swamy, A. S. and Shylashree, N

Subjects
*IMAGE compression, *HIGH dynamic range imaging, *VIDEOCONFERENCING, *VIDEO on demand, *MOBILE apps
Abstract

In High Dynamic Range Images (HDR), the illumination intensity levels vary over a very wide range and hence the storage space required is very large compared to normal Low Dynamic Range images. Transmission and distribution of HDR images and videos demand a large bandwidth coupled with higher communication overheads. Hence, image compression is invariably adopted for HDR images/videos so that they can be used efficiently in communication-intensive scenarios such as video conferencing and mobile applications. In this paper, a new method of lossless HDR image compression is presented that uses modulo encoding and subsequent reconstruction. [ABSTRACT FROM AUTHOR]

Published
2024
Full Text
View/download PDF

23. Review on Biosensors: Fundamentals, Classifications, Characteristics, Simulations, and Potential Applications

Author

Javalkar Vinay Kumar, Shylashree N, Seema Srinivas, Ajit Khosla, Hari Krishna R, and Manjunatha C

Abstract

Biosensor is a device which combines a physical transducer and biological active elements. The biological active element recognizes the specific analyte and produces biorecognized signal, which is further converted into a measurable signal by using an appropriate physical transducer. This review paper attempts in providing a comprehensive survey of the topic biosensor and due to its selectivity and sensitivity, biosensors are mostly widely used than other diagnostic devices. Because of its important features like selectivity, sensitivity, stability, reproducibility, linearity, and low cost, biosensors have a wide range of applications. This range includes their usage in disease detection, environmental monitoring, drug discovery, prosthetic devices, food safety, agricultural industry, and many more. Furthermore, this review discusses the various biosensors and its operations. Afterwards, with a summarized history of biosensors, further prospects have been described to present the usage of nanomaterials in biosensors. Various simulation software used to design the biosensor model are discussed in the end of the review.

Published
2022
Full Text
View/download PDF

24. Lossless Compression of Hyperspectral Imagery by Assimilating Decorrelation and Pre-processing with Efficient Displaying Using Multiscale HDR Approach.

Author

Anand Swamy, A. S., Mamatha, A. S., Shylashree, N., and Nath, Vijay

Subjects
IMAGE compression, HIGH dynamic range imaging, IMAGE reconstruction algorithms, BIG bands
Abstract

The instinctive essence of the Hyperspectral imagery cube is its immense information having both spatial and spectral correlation. In the interest of reducing the storage and bandwidth requisites, an effective lossless Hyperspectral compression system is proposed. The imagery is enforced to preprocessing stage preceding decorrelation. Preprocessing stage comprises band normalization and band ordering techniques. A technique named Greedy heap sorting is addressed to sort the bands. The proposed plan accords with a Compression ratio (CR) of 8.12 and bits per pixel (bpp) of 1.67. The performance of the system is comparable to earlier algorithms for lossless Hyperspectral image compression concerning compression ratio and bpp. An experiment conducted on AVIRIS images substantiates that the methodology presented surpasses the IP3-OBPS-BPS method by a percentage increase of 116.44 in CR and a percentage decrease of 58.49 in bpp. The multiscale High Dynamic Range (HDR) approach is used to project Hyperspectral images on devices with Low Dynamic Range (LDR) devices. The Bilateral filter is used for the decomposition of the image into multiple base layers and detail layer. The PSNR obtained is 37.4911 for the compressed HDR image, which signifies the better quality of the reconstructed image with a 4.8% compression ratio. [ABSTRACT FROM AUTHOR]

Published
2023
Full Text
View/download PDF

25. Modeling and simulation of cardio electrical activity for ischemia using comsol multiphysics tool

Author

Vinay Kumar Javalkar, Shylashree N, Yatish D Vahvale, Sridhar V, and Manjunatha C

Abstract

The circulatory system revolves around the heart, which is of blood vessels network that transports blood to all part of the body. All organs of human rely on blood for transport of oxygen and some other vital nutrients, ensuring that they remain good healthy and properly function. The heart is very important for blood pumping throughout the circulatory system. When the supply of blood to tissues is restricted, oxygen lack for cellular metabolism occurs (to keep tissue alive). Ischemia is a vascular disease in which arterial blood flow is interrupted to a tissue, organ, or extremity, resulting in tissue death if left untreated. It can be caused by embolism, atherosclerotic artery thrombosis, or trauma. Acute arterial ischemia can be caused by venous issues such as venous outflow blockage and low-flow conditions. One of the most common causes of acute arterial ischemia is an aneurysm. The importance of the heart structure on COMSOL Multiphysics is highlighted as it can be modeled and simulated for cardiac contraction and relaxation. The heart cavity structure is implemented using the FHN (Fitzhugh Nagumo equation) and LG (Landau Ginzberg equation) equations along with the corner cases in this paper. The model of the heart is divided into 4 different models to demonstrate the blood flow. The changes for the 4 models are in terms of mesh and the cavity change of heart structure which indirectly demonstrates the blood movement of the heart. The observed plots are in terms of spiral waves and also the waves for the dependent variables are plotted.

Published
2023
Full Text
View/download PDF

27. Comprehensive Design and Timing Analysis for High speed Master Slave D Flip-Flops using 18 nm FinFET Technology.

Author

Shylashree, N., Bharadwaj, Varchas S., Yashas, D., Kulkarni, Vinayak, Bharadwaj, Ajay, and Nath, Vijay

Subjects
*SETUP time, *FLIP-flops (Sandals), *TIMING circuits, *DIGITAL electronics, *ENSLAVED persons
Abstract

Ensuring correct functionality is the basic objective of any digital design and this can be done only if the circuit obeys all the timing constraints. Static Timing Analysis is the procedure performed to calculate the setup and hold time of any digital circuit and to check for any setup and hold time violations. This paper presents the methodology to perform setup and hold time analysis for different designs of Master Slave D Flip-Flop using 18 nm FinFET technology. FinFET technology was chosen since it is the prevalent technology in the industry. Implementation of D Flip-Flop design, suitable test circuit and timing analysis is performed on the Cadence virtuoso analog design environment tool. Using appropriate excitations, parametric analysis is carried out to obtain the setup and hold time values for various designs of D Flip-Flop including the proposed design. From the results, it was observed that the setup time and hold time varied with different clock edge rates. For the edge rates of 0.01, 0.05, and 0.1 ns, it was observed that the proposed design gave setup times of 54.9, 61.2, and 69.8 ps and hold times of −30.7, −43.6 and, −48.8 ps, respectively. On comparing all the results, it was observed that the GDI MUX and pass transistor-based designs gave a good trade-off between transistor count, setup time and hold time. For the proposed design, although the setup times were slightly on the higher side, the hold time values were more negative which is always preferred. [ABSTRACT FROM AUTHOR]

Published
2023
Full Text
View/download PDF

41. Ge4Sb1Te5 device case study for NVRAM applications.

Author

Shylashree, N., Sangeetha, B. G., Thonse, Adithya, and Nath, Vijay

Subjects
*THIN film devices, *PHYSICAL vapor deposition, *CASE studies, *TELLURIUM
Abstract

In this paper, the characterization of Ge4Sb1Te5 thin film device with 110 nm and 140 nm thickness was conducted. Fabrication was done using physical vapor deposition technique. The switching from amorphous to crystalline state is studied using electrical studies, whereas the Raman studies explains the structure of the film. The switching of the device is analyzed by current–voltage, resistance–voltage characteristics. Device endurance verifies this as an appropriate choice in the field of memory applications. [ABSTRACT FROM AUTHOR]

Published
2019
Full Text
View/download PDF

Catalog

Books, media, physical & digital resources
See catalog results