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We developed a monolithic integration process for a superconducting nanostrip single-photon detector (SNSPD) and a cryogenic signal processor based on a single-flux-quantum (SFQ) circuit. Sixteen-pixel SNSPDs consisting of a 10-nm-thick and 100-nm-wide NbTiN nanowire were fabricated on a 3-in. Si wafer with an SFQ merger fabricated by the National Institute of Advanced Industrial Science and Technology Nb 2.5 kA/cm2 standard process 2. Subsequently, we illuminated the photons on the 16-pixel SNSPD array through an optical fiber and obtained a similar bias-current dependence of the detection efficiency with a single-pixel SNSPD without the SFQ merger. This indicates that the SFQ merger works correctly, and that the power dissipation of the SFQ circuit, which is estimated to be 200 μW, does not deteriorate the photon detection of SNSPD fabricated on the same chip with a size of 5 × 5 mm2. Furthermore, we measured timing jitter using a pulsed laser as the photon source. Owing to the careful tuning of the wiring length between each pixel of the 16-pixel SNSPD and each input port of the SFQ merger, the obtained timing jitter was 41.4 ps, which is approximately equal to or less than that of the single-pixel SNSPD.

We discuss on the uncertainty relation (UR) for a closed one dimensional system (circle). In such a system, we cannot use the angle along the circle as a position variable. Otherwise we meet difficulties about the definition of the average position and the standard deviation (SD), and Hermitian property of angular momentum. From these reasons, we define the position variable as Cartesian variable $(X,Y)$ that have the periodic property for angle $\phi$. In the same way we define a SD by using that variables. Then we obtain two URs. We also discuss the minimum wave packet (MWP) on the circle. MWPs are expressed by von Mises distribution functions. Next we construct total URs by combining two URs for $X$ and $Y$. Furthermore, we extend the variables to $(X_n, Y_n)$ \; with $n= 1,2,3,\cdots$ and we have infinite series of total URs. We consider the meaning of such extended URs., Comment: 17pages. 5figures

An important figure of merit in microwave superconducting quantum interference device multiplexer (MW-MUX) is the quality factor of superconducting resonators. In advanced industrial science and technology (AIST), the intrinsic quality factor ${\boldsymbol{Q}_{{\mathbf i}}}$ of the resonators in the MW-MUX chips degraded significantly compared to those in the resonator-only chips owing to something during the fabrication process. In this study, we have investigated the damage process by conducting controlled experiments and an SEM-EDX analysis. As a result, we have confirmed that the metallic layers (Pd and Nb) were not removed completely and remained along the edge of the resonator, which resulted in the degradation of ${\boldsymbol{Q}_{{\mathbf i}}}$ . Further, we have invented a new process to overcome this imperfection during the removal of Pd layer using so called “caldera planarization”. The metal line that remained along the edge was not observed in the MW-MUX chips fabricated using this improved process. Finally, we have achieved ${\boldsymbol{Q}_{{\mathbf i}}}$ as high as that of resonator-only chips using the improved process.

Experimental demonstrations of quantum annealing with native implementation of Boolean logic Hamiltonians are reported. As a superconducting integrated circuit, a problem Hamiltonian whose set of ground states is consistent with a given truth table is implemented for quantum annealing with no redundant qubits. As examples of the truth table, NAND and NOR are successfully fabricated as an identical circuit. Similarly, a native implementation of a multiplier comprising six superconducting flux qubits is also demonstrated. These native implementations of Hamiltonians consistent with Boolean logic provide an efficient and scalable way of applying annealing computation to so-called circuit satisfiability problems that aim to find a set of inputs consistent with a given output over any Boolean logic functions, especially those like factorization through a multiplier Hamiltonian. A proof-of-concept demonstration of a hybrid computing architecture for domain-specific quantum computing is described., 12 pages, 11 figures

We are developing an x-ray imaging spectrometer for Super DIOS satellite mission, a future x-ray observatory, planned by JAXA, to be launched in 2030’s. Super DIOS will reveal the nature of the missing baryon in the warm-hot intergalactic medium because of its fine energy and angular resolution, large effective area and large field of view. A main detector on-board Super DIOS consists of a transition-edge sensor (TES) microcalorimeter array of over 30,000 pixels working at a temperature below 100 mK and it poses a considerable technical difficulty to the readout. A microwave superconducting quantum interference device (SQUID) multiplexing is promising technique and expected to achieve a large scale readout of more than 30,000 pixels. We describe our development of a 40-channel microwave SQUID multiplexer with low-noise characteristics∗ and a demonstration of simultaneously reading out 40-pixel TESs. Finally, we discuss a future prospect and a feasibility of reading out an array of more than 30,000 pixels.

The quality factors and noise performances of superconducting resonators play an important role in microwave SQUID multiplexer (MW-MUX). Since we develop microwave SQUID multiplexer for transition edge sensor arrays, the operation temperature is around 100 mK where the effects of two level system (TLS) can be significant. In this paper, we have investigated the electrode-material or wafer dependence of noise performance of MW-MUX by characterizing four types of resonators. Although the temperature dependence of resonance frequency and the power dependence of ${{\boldsymbol{Q}}_{\boldsymbol{u}}}$ show clear difference among the materials, frequency noises which contribute the readout noise of MW-MUX are similar. Theoretical model predicts that not TLS but other loss dominates ${{\boldsymbol{Q}}_{\boldsymbol{u}}}$ in the power region suitable for the low-noise operation of our MW-MUX. Further, the estimated flux noise calculated from the measured frequency noise and the conversion coefficient from frequency to flux were 1–5 $({{{\mathbf \mu }}{{{\mathbf \Phi }}_0}/\sqrt {{{\mathbf Hz}}} })$ @ 1 Hz, 0.2–0.8 $({{{\mathbf \mu }}{{{\mathbf \Phi }}_0}/\sqrt {{{\mathbf Hz}}} })$ @ 3 kHz. These results indicate the noise of our MW-MUX has small material dependence and the compatible low noise operation to typical dc SQUIDs would be possible. Therefore, the MW-MUX with our materials would not suffer from the low frequency noise due to TLS.

In order to read out current signals from large-scale arrays of transition edge sensors (TES), microwave SQUID multiplexers (MW-MUX) have been developed by several groups. Reduction of crosstalk induced in the multiplexer is important in order to maintain the energy resolution or the noise equivalent power of detector arrays. In the present study, crosstalk between channels in MW-MUX with five different designs is experimentally evaluated. The resonance frequency separation is ten times as large as the resonator bandwidth. Without flux-ramp modulation, crosstalk between two adjacent channels neighboring in position decreases to ≍1 × 10–3 with increasing resonance frequency separation to ≍100 MHz. Crosstalk between SQUID channels neighboring in resonance frequency also decreases to 4 × 10–3 with increasing the distance to 2.5 mm. We show that nonlinear error can occur due to the crosstalk with flux-ramp modulation. Flux readings from a well-designed multiplexer exhibit crosstalk of less than 1 mΦ0 peak-to-peak and nonlinear errors of less than 2 mΦ0 peak-to-peak, which is sufficient for the readout of the gamma-ray TES arrays being developed. These results can provide guidelines for suppressing both the crosstalk and the nonlinear error to less than the criterion of TES spectrometers with typical energy-resolving ability.

Critical state field profiles and thermomagnetic instabilities are studied in two kinds of three-dimensional nanostructured superconductors. We find that the critical state field profiles in some simple bi-layer systems are not simple superpositions of critical states in the two layers. Competition between the divergence of the local field at the edges of the film and the shielding by the neighboring layer makes novel critical state field profiles. We also studied flux avalanches in shifted strip arrays (SSAs) with layer numbers up to six. Various forms of avalanches either perpendicular or parallel to the strip are observed when the overlap between strips in neighboring layers is large. We also find that introduction of asymmetry in various forms to SSA affects the shape of flux avalanches sensitively.

著者人数: 14名, Accepted: 2016-02-17, 資料番号: SA1150322000

Accepted: 2016-02-17, 資料番号: SA1150323000

We report very-low-noise, fast-response, middle-scale multiplexing in a microwave superconducting quantum interference device multiplexer (MW-Mux) as a transition-edge sensor (TES) readout. Our MW-Mux is able to read 40 channels with 500 kHz sampling and has a low readout noise of 0.9 μ Φ 0 / Hz (where Φ 0 is the magnetic flux quantum), equivalent to 9 pA / Hz. By contrast, a multiplexer of less than 10 pixels with 500 kHz sampling and ∼ 2 μ Φ 0 / Hz readout noise has so far been reported in the literature. Owing to the 500 kHz sampling, our MW-Mux exhibits a fast response to detect a TES pulse with a rise time around 12 μ s. We demonstrated simultaneous readout of 38 pixels from an array of x-ray TES microcalorimeters. The measured full-width values at half-maximum spectral resolution ranged from 2.79 to 4.56 eV, with a median value of 3.30 eV at 5.9 keV, including a ∼ 10 % contribution of readout noise, i.e., 0.9–1.7 eV.

We have fabricated multi-layer superconducting shifted strip arrays (SSAs) of Nb up to 4 layers and systematically studied the vortex penetrations into these structures. We observed the vortex penetration as a function of the number of layers and the ratio of overlap between neighboring layers by using magneto-optical (MO) imaging. In the case of 2- and 3-layer SSAs, spot-like avalanches occur when the overlap is small, while linear avalanches occur when the overlap is large, consistent with our previous reports. In the 4-layer SSAs, the smallest limit of the overlap between the neighboring layers for the linear avalanche is lower. Flux penetrations parallel to the strip which were observed in the 3-layer SSA were also observed in the 4-layer SSAs with smaller ratio of overlap. Larger demagnetization effects in the middle two layers in 4-layer SSA help to make avalanches larger and more extended.

We designed and fabricated rapid single-flux-quantum (RSFQ) circuits using a new 20-kA/cm 2 process based on conventional Nb/AlO x /Nb Josephson junction (JJ) technology. Circular JJs were fabricated to improve their uniformity. They had sufficiently low spread of the critical currents for large-scale RSFQ circuits. We selected the circuit design parameters carefully, including the bias voltage and McCumber-Stewart parameter, balancing the energy consumption, switching speeds, margins, and integration density. We demonstrated several logic gates and shift registers at a clock frequency of 154 GHz with the designed bias voltage of 2.5 mV, and demonstrated energy-efficient shift registers using the low-voltage RSFQ (LV-RSFQ) technique at 83 GHz.

We propose a prime factorizer operated in a framework of quantum annealing (QA). The idea is inverse operation of a multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality. The invertible operation of QA logic gates consisting of superconducting flux qubits was confirmed by circuit simulation with classical noise sources. The circuits were implemented and fabricated by using superconducting integrated circuit technologies with Nb/AlOx/Nb Josephson junctions. We also propose a 2.5Dimensional packaging scheme of a qubit-chip/interpose /package-substrate structure for realizing practically large-scale QA systems., Comment: 17 pages, 11 figures

We have fabricated two- and three-dimensional nanostructured superconductors, and observed vortex penetrations by magneto-optical imaging. In the case of two-dimensional superconducting networks with square holes on a square lattice, anomalous diagonal penetrations are widely observed. Two kinds of diagonal vortex penetrations at high and low temperatures have been interpreted as originating from the repulsive interaction of vortices and sharp fan-shaped vortex penetration from the corners of the square holes, respectively. In the case of three-dimensional stack of superconducting strip arrays with double and triple layers, vortex avalanches have been observed in a wide temperature and dimension ranges due to enhanced demagnetization effect. While spotlike avalanches are observed when the overlap of strips is small, anomalous linear avalanches traversing many strips in different layers are observed when the overlap is large. In triple-layer strip arrays, in addition to the spotlike and linear avalanches, vortex penetrations along the line of strips are also observed. Origins of the anomalous diagonal penetration and vortex avalanches are discussed.

Accepted: 2013-12-17, 資料番号: SA1004633000

International audience; We investigate the magnetic field and current distributions in structures made of superposed supercon- ducting films. A recent experimental study of a planar bilayer structure (Tamegai 2017) has revealed unusual pat- terns in the critical state, with an unexpected discontinuity line arising in the region where the layers overlap. We use a finite element model to investigate the critical states in such 3D structures with several layers and different overlapping configurations. We show that the experimentally observed discontinuity line arises as a result of a magnetic field dependence of the critical current density. Additionally, we show that the network of discontinuity lines not only depends on the geometry of the system but also evolves with the applied magnetic field as the structures are magnetized in a zero-field-cooled mode. The strength of the magnetic coupling is shown to depend on the number of layers, their overlap and separation, with a direct effect on the length and the shape of the discontinuity lines.

We have fabricated three-dimensional double- and triple-layer strip arrays of Nb and observed flux penetration into these strip arrays with an applied field perpendicular to the plane by using the magneto-optical imaging method. In the triple-layer strip arrays with large overlaps between the strips, we observed flux avalanches and one-dimensional penetrations perpendicular to the strip similar to the case of double-layer strip arrays. In thicker triple-layer samples, we also observed flux avalanches parallel to the strip. Enhanced demagnetization effect, thermal conductivity between the neighboring layers, and the driving force parallel to the strip are believed to cause these avalanches.

We have fabricated three-dimensional double-layer strip arrays of Nb and observed flux penetrations into these strip arrays with applied field perpendicular to the plane by using the magneto-optical imaging method. In strip arrays with large overlaps between strips we observed flux avalanches even at 1.5 K below the critical temperature. Novel flux avalanches showed up as one-dimensional penetrations perpendicular to the strip arrays in samples with the maximum overlap. Enhanced demagnetization effect and thermal conductivity between the top and bottom layers are believed to cause these avalanches.

Accepted: 2017-05-02, 資料番号: SA1170002000

The origin of the anomalous diagonal flux penetration is investigated in Nb square superconducting networks. The magnetic field dependence and heat transfer coefficient dependence of this phenomenon are observed by using the magneto-optical imaging method. The anomalous diagonal flux penetration occurs independent of the applied magnetic field. Flux avalanches at low temperatures are suppressed by depositing a thick gold layer due to the enhancement of the thermal conductivity. However, the diagonal flux penetration appears even in the area covered by the gold layer. Combining these observations, we conclude that flux avalanches do not promote the diagonal flux penetration.

We have reported that vortex penetrations into superconducting square networks with square holes show anomalous diagonal patterns [1] , [2] . In order to get more insight into the origin of this phenomenon, we have made magneto-optical imaging of new sets of network samples fabricated from Nb; (1) square networks with square holes with different film thicknesses, (2) square networks with different shapes of holes, (3) square networks with square holes and anti-dots at the center of intersections. These measurements are compared with electromagnetic simulation of a model system, and possible origins of the anomalous vortex penetration are discussed.

We have observed flux penetrations into square superconducting networks of Nb with various thicknesses and hole-shapes by using magneto-optical imaging method. The penetrated pattern does not depend on the thickness and extends along diagonal direction when the samples have smaller area in the intersection of networks. We have also observed similar superconducting networks with and without small holes at the intersection. The small holes at the intersection do not work as a promoter for the diagonal flux penetration though the parallel flux penetration becomes weak. We discuss possible origins of these anomalous anisotropic flux penetrations.

A cryogenic current comparator (CCC) is an instrument of great importance in electrical metrology, which provides a ratio of two currents with ultimate accuracy based on superconductivity. It is used for dc resistance calibration in many national metrology institutes. Conventional CCCs consist of multi-turn coils of wire windings, a multi-layered shield of superconductor foils and a separate SQUID sensor. This implementation results in a bulky device too massive to cool with a mechanical cryocooler, making a system inconvenient. A new implementation of CCC, an integrated CCC (ICCC) consisting of thin-film spiral coils, a thin-film superconducting shield and a SQUID sensor integrated on a single chip, enables a user-friendly system operated with a compact cryocooler. Prototype ICCC chips were designed and fabricated by using a superconducting Nb integrated circuit technology with chemical-mechanical polishing. The basic operation of the prototype ICCCs was confirmed by monitoring periodic flux-voltage characteristics of the SQUIDs.

We have been developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. The SFQ floating-point adder (FPA) is one of the principal and most complicated circuit blocks in an LSRDP. In this study, we designed and implemented component circuits of an SFQ bit-serial half-precision FPA using the cell library for a 10-kA/cm2 Nb process and performed on-chip high-speed tests. We demonstrated correct operation of the four-bit shifter for the significand at the clock frequencies of up to 76 GHz. The dependence of the measured DC bias margin on the operating frequency agrees reasonably well with the margin calculated using a digital simulation. The operation of the normalizer for the significand has been also confirmed at low speeds.

This paper reports the design and test results of a single-flux-quantum (SFQ) bit-serial adder, which we designed with a target-clock frequency of 100 GHz, to investigate several techniques for producing ultra-high-speed computations using SFQ circuits. The bit-serial adder was designed based on a new cell library developed for the ISTEC Advanced Process, where the critical current density and McCumber-Stewart parameters of Josephson junctions were increased to 10 kA/cm2 and 2.0, respectively, to obtain higher operating frequencies. In addition, we adopted a circuit-design technique based on state transitions excluding a feedback loop in a typical bit-serial adder, and redesigned the NOR gate with the McCumber-Stewart parameter increased to 4.0 to improve performance. As a result, we experimentally obtained a sufficient dc bias margin of ±18% from low frequencies to 60 GHz, and verified the correctness of operations up to 93 GHz. We also demonstrated that the introduction of a higher bias voltage or large inductors in series with bias resistors is effective for achieving faster operation.

We have estimated jitter accumulated in data and clock lines of an SFQ Reconfigurable Data Paths processor and its impact on the operating frequency and identified critical components. In order to prevent performance degradation, we have proposed to divide the processor in several parts clocked separately by an external jitter-free system clock. FIFO buffers and clock controllers inserted between the processor stages are used to synchronize each stage with the next one and as a result the accumulation of jitter is limited to one stage of the processor only. Two versions of a synchronization scheme prototype have been designed for both ISTEC-SRL standard 2.5 kA/cm2 and advanced 10 kA/cm2 processes and successfully tested at high speed.

We investigated the most suitable device structure for large-scale SFQ circuits and propose a new Nb 10-layer device structure that is composed of active layers including junctions at the top, PTL layers in the middle and DC power layers at the bottom. This device structure enables us to reduce the influence of the magnetic field due to large bias currents and to form a Nb/AlOx/Nb junction layer in the last part of the fabrication sequence. To achieve this structure, we developed a higher quality planarization that could remove the residual slight roughness after standard caldera planarization. We fabricated a diagnostic chip that is composed of test elements such as junctions, contacts, resistors and many kinds of process test patterns. We obtained sufficient characteristics for the diagnostic chips. Moreover, to evaluate the fabrication process, we designed and fabricated several shift registers. We confirmed the correct operation of an up to 2560-bit shift register having 10,281 junctions.

We are developing a large-scale reconfigurable data path (LSRDP) using single-flux-quantum (SFQ) circuits as a fundamental technology that can overcome the power-consumption and memory-wall problems in CMOS microprocessors in future high-end computing systems. An SFQ LSRDP is composed of several thousands of SFQ floating-point units connected by reconfigurable SFQ network switches to achieve high performance with low power consumption. In this study, we designed and implemented an SFQ floating-point multiplier (FPM), which is one of the key components of the SFQ LSRDP. We designed a systolic-array bit-serial half-precision FPM using the 2.5 kA/cm2 Nb process. The resultant circuit area and number of Josephson junctions are 6.22 mm times 3.78 mm and 11044, respectively. The designed clock frequency is 25 GHz. We tested the circuit and confirmed the correct operation of the FPM by on-chip high-speed tests.

We have developed an advanced process for fabricating a next-generation multi-layer Nb integrated circuit structure incorporating a top active layer. In this structure, the passive-transmission-line (PTL) layer is placed between the top active layer and a DC-bias current layer at the bottom. This structure will make it possible to flexibly design active circuits and PTL wiring, and will also enable active circuits to be effectively shielded from magnetic fields generated by a large DC-bias current. Both the DC-bias current layer and the PTL layer are planarized; however, the top active layer is fabricated without planarization. To fabricate this new structure, it was necessary to achieve a better planarization process for junctions formed over underlying Nb patterns. The combined process we developed comprising additional SiO2 deposition and additional mechanical polishing after the standard Caldera planarization process results in superior planarization for junction formation. We obtained excellent characteristics of junctions formed over underlying pattern edges when they were fabricated on surfaces planarized using this new process. Using the process, we fabricated new 10-Nb-layer integrated circuit structures and estimated the characteristics of their circuit elements.

Josephson junctions with niobium electrodes connected with palladium, which is employed in the bump metallization, have about 20% larger critical current density than those with electrodes not connected with palladium. This increase in the critical current density coincides with the desorption of hydrogen from the niobium electrodes. Hydrogen incorporates during the fabrication process and desorbs in an atmosphere when the niobium surface is covered with palladium. The decrease in hydrogen concentration in niobium electrodes causes an increase in the critical current density of the junctions. Most of the change can be attributed to the niobium work function change, with some of it due to the change in superconductivity of niobium. Elastic deformation can also be added as a cause. As hydrogen diffuses fast in niobium and stops in aluminum, hydrogen concentration differences arise within a circuit, which result in a critical current deviation beyond statistical scattering. This mechanism explains why the junctions at both ends of a serial array of circuits exhibit abnormal critical current about 20% larger than the average.

We have studied single-flux-quantum (SFQ) propagation properties in passive transmission lines (PTLs) based on a 10-Nb-layer device structure (ADP2). In ADP2, we can use the PTLs with a line width about 5 mum, one seventh of conventional line width by adopting a strip line (SL) structure and increasing the characteristic impedance. The evaluation has been conducted on the PTL length and the via-hole structure by using ring oscillators. We found that the decrease in the operating region was larger for longer PTL, compared with that in a conventional device structure (STD2). The results would be caused by the increase in the surface resistance. The via-holes connecting the PTLs on different layers have more complicated structure than those of STD2. We have designed the via-hole structure using the electromagnetic wave simulator HFSS. As a result, we have demonstrated sufficiently large operating margins at any data rates up to 80 Gb/s even for the ring oscillator with 30 via-holes.

We have evaluated the effects of a DC power (DCP) layer in a 10-Nb-layer device using SQUIDs and large-scale Josephson transmission lines (LS-JTLs). The 10-Nb-layer device has recently been developed for SFQ LSIs, with an active layer including Josephson junctions (JJs) at the top, two passive transmission line layers in the middle, and the DCP layer for bias current feeds at the bottom. The evaluation with SQUIDs revealed that the 10-Nb-layer device structure drastically reduced the magnetic flux induced by DC currents flowing through the DCP line, in comparison with the previous advanced process device structure. A major factor for this reduction was an increase in the number of ground layers between the DCP layer and the active layer. In the test of the LS-JTLs containing about 12000 JJs, we obtained the operating margins as wide as numerically simulated ones. We also observed no difference in the margins between a method for extracting ground return currents through ground layers and that through the dedicated layer. These results demonstrated that the 10-Nb-layer device structure is suitable for SFQ-LSIs.

We are developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. In the LSRDP, an SFQ floating-point adder (FPA) is one of the main and most complicated circuit blocks. In this paper, we designed and implemented an SFQ half-precision FPA and carried out on-chip high-speed tests. The data format of the half-precision FPA obeys the IEEE standard, in which two input data streams, an 11-bit significand and a 6-bit sign/exponent, are processed bit-serially. The floating-point addition is performed by three steps: (1) alignment and rounding of significands, (2) addition/subtraction of the significands, and (3) normalization of the result. We implemented an SFQ half-precision FPA using the SRL 2.5 kA/cm2 niobium standard process. The size, power consumption and total junction number are 5.86 mm times 5.72 mm, 3.5 mW and 10224, respectively. The simulated DC bias margin is plusmn20% at 20 GHz operation, which corresponds to the performance of 1 GFLOPS. We successfully confirmed the correct operation of the FPA except a read-out circuit for the significand at 24 GHz by on-chip high-speed tests.

We have investigated the effect of a dc-power (DCP) layer on the performance of single flux quantum (SFQ) circuits by changing the film thickness of a ground plane (GP). The DCP layer was placed below the GP and was used as bias current feeds. Two measurements were conducted. One was direct detection of the magnetic flux above the GP by using SQUIDs. The results indicated that the GPs with film thicknesses of more than 400 nm were effective to completely suppress the flux under the condition that the return current was extracted from the ground plane. The other was evaluation of the operating margins of the 408 bit shift register circuits (SRs) with 8032 Josephson junctions and a total designed bias current of 1.05 A. The results showed that a 500 nm thick GP had an advantage over a 300 nm thick GP in the dependence of the upper margin on the bias current port of the SR.

We have developed an advanced fabrication process for fabricating Nb integrated circuits with up to nine planarized Nb layers, and with critical current density of Josephson junctions of 10 kA/cm2. We have continued to improve this advanced process. For nine-layer integration, we readjusted film thickness of Nb and SiO2 layers in order to reduce the strain of films and substrate. Total film thickness of the nine-Nb layered structure was about 3 mum; this was kept nearly as thin as that of the six-Nb-layered structure. The resulting thinner SiO2 layers enabled narrower passive transmission line wiring, which had the advantage of smaller occupation area. The room temperature measurement of process monitoring patterns is useful for screening defective wafers in the middle step of the process. For higher circuit reliability, we modified fabrication processes such as junction planarization. As a result, the reliability of SiO2 insulation between an upper and a lower Nb wire adjacent to a Josephson junction was improved.