Search

The high failure rate of semiconductor devices and capacitors, matched with their high requirement in the architecture of a multilevel inverter (MLI) topology, results in low reliability of the inverter. A low device count, preserving the output power upon fault occurrence and the ability to tolerate both open- and short-switch failures on all fault locations, handling both single- and multiple-switch failures, and achieving natural voltage balancing of the capacitors, are the main challenges for the existing solutions to the fault-tolerant topologies. Thus, a highly resilient fault-tolerant topology, based on conventional inverters, is proposed in this article. The proposed solution accomplishes all the aforementioned challenges without deteriorating the efficiency of the inverter during faulty conditions. The robustness and effectiveness of the proposed topology are verified by the obtained experimental results. Multiple cases of switch failure are considered to cover all fault locations and types. Comparative analysis with the recently proposed fault-tolerant topologies on MLIs shows the superiority of the proposed topology over the rest.

This article presents a single-phase symmetrical and asymmetrical multilevel inverter (MLI) topology. The presented topology can generate 9-level output voltage in a symmetrical configuration and 13- and 17-level output voltage in asymmetrical configuration with a single cell. The number of output levels can be improved further by increasing either the number of cells or switches in a single cell. The presented topology contains the least number of dc sources, semiconductor switches, capacitors, and diodes compared with classical and recently proposed topologies. Reduction in component count decreases the size, complexity, and cost of the overall converter. A detailed comparison has been done of the presented topology with the recently proposed topologies in terms of dc sources, semiconductor switches, capacitor, and total blocking voltage. Finally, to validate the presented concept, the prototype of the presented 9-, 13-, and 17-level MLI topologies has been tested in the laboratory for different switching frequencies, different modulation indexes, sudden load changes, and nonlinear load.

The redundancy in switching states to generate different voltage levels is of great importance to incorporate fault-tolerant features in multilevel inverters. However, this redundancy comes at the expense of high device count, which is paralleled with vulnerable characteristics of semiconductor devices, resulting in low reliability. About this concern, the present study introduces a novel fault-tolerant topology to generate the five-level output voltage. The proposed topology can tolerate open-circuit failure, for single and multiple switches with the help of novel redundant leg architecture and short-circuit condition is dealt with the fast fuses. The comparative study with recent literature is discussed, which reveals the superiority of the proposed topology, in terms of qualitative as well as quantitative parameters. Switching strategies are proposed under different single and multiple switch fault cases, which achieves self-balancing of capacitor voltage. Thus, no complex control scheme is required. The simulation is performed in MATLAB/Simulink, and the feasibility of the proposed topology is validated using experimental results.

Multilevel inverters (MLIs) have gained significant recognition in the field of high-power conversion due to its reduced voltage stress across the power switches and low total harmonic distortion in the output voltage waveform. However, MLI incorporates a large number of semiconductor switches and isolated dc sources, which increases its cost and complexity and reduces the reliability. In this paper, a novel topology of MLI is proposed for both symmetrical and asymmetrical configurations. The proposed configuration offers a reduced number of controlled switches and dc source as compared to conventional and recently proposed topologies. Reduction in switches and dc sources reduces the cost, size, and complexity and enhances the overall performance of the proposed topology. A comparative analysis of the proposed topologies with the classical topology and recently published topologies have been made in terms of controlled switches, power diodes, driver circuit requirement, dc voltage sources, and blocking voltage. Multicarrier pulsewidth modulation strategy is adopted for generating the switching pulses. The detailed simulation study of the proposed topology has been carried out using MATLAB/SIMULINK and feasibility of topology has been validated experimentally for 5-/25-level inverter.

Photovoltaic (PV) systems, especially which are installed in the remote areas, stand in need for a highly reliable system. A high failure rate of the semiconductor switches and capacitors yields a very low reliability of the inverters used in the PV system. Conventional two-level inverters are replaced by multilevel inverters (MLIs) to effectively improve the output quality waveform. However, MLIs incorporate a high device count in their architecture which further impairs the reliability of the PV system. Recent research has focused on developing fault-tolerant MLI topologies with reduced device count. However, the number of active devices and power losses, factors which are many of the times overlooked, are key in determining the reliability of the inverter. Here, the reliability of a novel fault-tolerant MLI topology is evaluated bearing in mind the effect of power losses on the junction temperature. Equal (or best) voltage source utilisation characteristics help in maintaining the uniform charge of the batteries. The concept of reliability is evaluated mathematically. The fault tolerance and even source utilisation of the proposed topology is verified through the obtained experimental results.

Multilevel inverters (MLIs) have developed deep roots in various industrial sectors owing to their advantages over conventional two-level inverters. However, the reliability of the semiconductor devices has been one of the major concerns for the proper functioning of MLI. Therefore, a novel fault-tolerant topology is proposed in this study. The proposed topology is capable to tolerate single- and multi-switch faults. It has lesser device count compared with the most recent work in the field. Moreover, it achieves inherent voltage balancing across capacitors. The proposed fault-tolerant topology is simulated in MATLAB/Simulink and validated experimentally.

In this study, two new structures of single-phase hybrid multilevel inverter are proposed for both symmetrical and asymmetrical configurations that can be employed in drives and control of electrical machines and connection of renewable energy sources. The proposed configuration uses a less number of semiconductor devices and DC sources as compared with conventional and newly developed topologies which lead to a reduction in cost and installation area. The proposed topology poses a vital advantage of self-voltage balancing of its capacitor voltage regardless of load type, load dynamics and modulation index. Also, the proposed topology is expanded in a cascaded fashion which reduces the complexity and improves the performance significantly. A wide range of comparison is done with conventional and newly developed topologies to show the superior performance of proposed topologies regarding a total number of switches and DC sources. The multi-carrier pulse-width modulation strategy is adopted for generating switching pulses for respective switches. A laboratory prototype is developed for testing the performance of the proposed topology for 9-level and 17-level inverters.

Reduced voltage stress and low-total harmonic distortion are the main causes for such widespread application of multilevel inverters (MLIs) in various industrial sectors. However, reliability is one of the major concerns of MLIs as it uses a large number of switches as compared with two-level inverters. Therefore, a newly developed transistor clamped H-bridge inverter is proposed in the literature which uses a relatively less number of switches and DC sources as compared with cascaded H-bridge but lacks in reliability due to the absence of redundant states. Hence, in this study, the reliability improvement strategy for newly developed five-level transistor clamped H-bridge-based cascaded inverter is proposed which can be generalised for any number of levels. In the proposed fault tolerant strategy, the fault can be broadly classified based on the two main legs of the proposed inverter. Moreover, the proposed fault tolerant strategy does not require any kind of external circuit for maintaining its capacitor voltage in the balanced state. Finally, to validate the concept, a laboratory prototype of the five-level inverter is developed and results are obtained successfully.

Low reliability is one of the major concerns of multilevel inverter due to the requirement of a large number of semiconductor devices as compared to two-level inverters. Thus, in this paper, a novel topology of multilevel inverter is proposed that can tolerate both open and short-circuit faults on its switches. The proposed topology also reduces dc sources and capacitors as compared to the conventional and recently proposed fault-tolerant topologies. Two types of solutions are provided in order to make the proposed topology fault tolerant; first provides a partial solution to fault, while the second provides a complete solution to fault. In addition, a novel switching strategy is proposed to reduce the amount of capacitor voltage ripples under normal and postfault conditions. Also, the proposed switching scheme offers an additional advantage of self-voltage balancing of its capacitor voltage both under normal as well as postfault conditions. To validate the proposed concepts, simulation and experimental analysis are carried out and different results are presented to show the viability of the proposed topology under normal operation, during fault and postfault conditions.

In DC/AC power conversion, multi-level inverter (MLI) incorporates a large number of semiconductor devices, which increases its cost and complexity. Moreover, the recently introduced topology uses a large variety of semiconductor switches. Therefore, a great attention is paid toward increasing output voltage levels with less variety and reduced number of switches as compared to conventional topologies. In this paper, improved configuration of symmetrical and asymmetrical MLI is proposed. Improvement is brought on both quantitative and qualitative basis, which led to a reduction in number of semiconductor devices and its variety. Analysis of power losses of the proposed topology is carried out and compared with CHB. A wide range of comparison with recently proposed topologies is made in order to show the novelty and contribution of the proposed topology. Multi-Carrier Pulse Width Modulation strategy is adopted for generating the switching pulses. The detailed simulation study of the proposed topolo...

The use of medium frequency allows the transformer size to be reduced at the higher power level. Reduction in size of the transformer leads to a reduction in installation area which is of prime concern in many renewable energy resources. But the reduction in size at higher power level comes with the cost of higher loss density and lower thermal stability. Therefore, this paper deals with the various constraints and considerations that are required to be taken care of while designing the medium frequency high power transformer (MFHPT). This paper also provides the optimal design of transformer w.r.t. frequency and power. For analysis and comparison purpose, both core and shell type design is developed in Ansys Maxwell (Ver. 16) for 3 MVA transformers at 1000 Hz of frequency using nanocrystalline core material.

Low reliability of semiconductor switches result in the maloperation of the multilevel inverter (MLI). In order to gain the advantages offered by the MLI without compromising on the reliability, a fault tolerant topology of MLI is required. In this paper, the switched capacitor MLI (SCMLI) structure is explored to extract its inherent capacity for single switch and multiple switch failure. In order to incorporate fault tolerant characteristics to a 9 level SCMLI structure, the outermost capacitor is substituted by the DC voltage source. This results in the ability of the SCMLI to tolerate both single and multiple switch failure across all its level generating switches. Proper implementation of the switching scheme results in inherent capacitor voltage balancing. All the employed switches in the architecture of the topology of main inverter are fault tolerant. Least modification in the switching scheme after fault occurrence and less number of active switches makes the modified SCMLI topology more reliable with reduced device count. Assessment of the viability and robustness of the topology is verified through MATLAB simulation and experimentally validated using real-time simulator, OPAL-RT.

Multilevel inverter (MLI) is receiving remarkable recognition due to its reduced voltage stress across the power switches and low total harmonic distortion in output voltage. However, MLI incorporates large number of semiconductor switches and hence increases its complexity. In this study, new structures of symmetrical and asymmetrical MLI are proposed. The proposed structures offer reduced number of controlled switches, power diodes, capacitors and DC sources as compared with classical and recently proposed topologies in the line. Reduction of switch count, driver circuit and DC voltage sources reduces the size, cost, complexity and enhances overall performance. Moreover significant reduction in voltage stress across the switches can be achieved. A comparative analysis of proposed topologies with the classical topology and recently published topologies has been made in terms of controlled switches, power diodes, driver circuit requirement, DC voltage sources and blocking voltage. Multi-carrier pulse width modulation strategy is adopted for generating the switching pulses. The detailed simulation study of the proposed topology has been carried out using MATLAB/Simulink and feasibility of topology has been validated experimentally.

The interest in development of newer topologies of multilevel inverter has been increasing rapidly in past few years. Recently introduced topologies achieve higher number of output voltage steps with reduced number of switches, DC voltage sources, voltage stress across switches and losses as compared with the conventional topologies. In this study, a new structure of symmetrical multilevel inverter is proposed. The proposed structure offers reduced number of controlled switches, power diodes and DC sources as compared with classical and recently proposed topologies in the literature. Reduction of switch count and DC voltage sources reduces the size, cost, complexity and enhances overall performance. Proposed topology is capable of producing 7, 9 and 11 levels of output voltage with seven switches only. Moreover, significant reduction in voltage stress across the switches can be achieved. A comparative analysis of proposed topology with the conventional topology and recently published topologies has been made in terms of controlled switches, power diodes, driver circuit requirement, DC voltage sources and blocking voltage. Multi-carrier pulse-width modulation strategy is adopted for generating the switching pulses. Simulation study of the proposed topology has been carried out using Matlab/Simulink and feasibility of topology has been validated experimentally.

Multilevel Inverters (MLI) faces severe performance limitation owing to the low reliability of the power electronic devices and capacitor voltage balancing. Therefore, a novel fault tolerant MLI topology is proposed in this paper. The proposed topology can sustain single and multiple switch fault on all of its main inverter switches. The switching scheme opted results in inherent DC-link capacitor voltage balancing and equal (or best) voltage source utilization, under both healthy and faulty conditions. The validity of the proposed topology is verified by the obtained OPAL-RT results.

Proper functioning of the Multilevel Inverter (MLI) is dependent on the healthy performance of its power electronic components. Amongst all power electronic components, power electronic switches and capacitors are most prone to faults. Thus, a failure on these devices may lead to undesired outcomes or even complete shutdown of the application. Thus, the development of a highly reliable MLI topology which is able to deliver the desired output, during worst faulty conditions, has become a recent research trend. In this paper, a novel fault tolerant MLI topology is proposed which is able to sustain single switch failure on all of its main inverter switches. Not only that, the proposed topology is able to achieve inherent DC-link capacitor voltage balancing. The reliability of the proposed topology is analyzed mathematically. The validity of the proposed topology is verified by the obtained OPAL-RT results.

In applications using multilevel inverter topology, low reliability is one of the biggest concerns since a large number of semiconductor devices are used. Semiconductor devices are the weakest link in the power inverter system. Therefore, fault tolerance control becomes necessary where human intervention is least possible. In this paper, a novel topology is proposed which is fault tolerant to open switch faults and delivers power uninterruptedly. The fault tolerance has been achieved by adding additional but a minimum number of switches required. The proposed topology shows better results when compared with the recently proposed topologies. The switching scheme employed exploits the redundant paths in such a way that leads to the self-voltage balancing of the capacitors under healthy and faulty conditions. The validity of the proposed open switch fault tolerance is verified through simulation results.

The retinoblastoma susceptibility gene RB-1 is a tumour suppressor gene that encodes a protein (Rb) that regulates the transition from the G1 phase to the S phase of the cell cycle. Inactivation of the Rb gene has been shown in a variety of human tumours, including breast, ovarian, hepatic, prostatic, and endometrial carcinomas. Although Rb protein is normally expressed in the nuclei of healthy cells, during carcinogenesis there is a partial or complete loss of nuclear expression. Recently, some reports have indicated aberrant cytoplasmic expression of Rb protein. However, little is known about its cytoplasmic expression and significance as a prognostic marker in canine mammary tumours (CMT). The present study was performed on 36 malignant CMT cases in order to assess the mutational status and prognostic significance of Rb in primary malignant CMT. We report an almost complete loss of nuclear expression of Rb protein with corresponding gain of aberrant cytoplasmic expression in basal/myoepithelial cells in CMT. Strikingly, our analysis reveals a significant positive correlation between survival time and cytoplasmic expression of Rb protein in basal cells. Moreover, cytoplasmic expression of Rb protein in basal cells was also correlated with tumour grade and stage.

Multilevel Inverter (MLI) is a key player in high-power high-voltage applications. However, MLI requires large number of semiconductor switches, gate driver circuits and diodes in order to perform its conversion. Besides this, MLI also has a very complex controlling technique. Hence, in order to overcome the above mentioned problems, a new symmetrical topology of MLI is proposed in this paper which requires less number of switches, driver circuits and diodes as compared to conventional topologies and other recently proposed topologies. A comprehensive comparison is done between the proposed and other topologies. Multi-Carrier Pulse Width Modulation (MCPWM) technique has been used for controlling purpose, in which number of carrier signal is also reduced to half when compared with conventional topologies. The complete simulation study of the proposed topology has been carried out using MATLAB/SIMULINK and feasibility of topology has been validated experimentally.

MLI is receiving tremendous popularity due to its reduced voltage stress across switches and low THD in output voltage. MLI incorporates large number of semiconductor switches which increases complexity and reduces efficiency. Therefore, a great deal of attention is paid towards reducing the number of semiconductor switches. The reduction of switch count reduces the size, cost and complexity and enhances overall performance. In this paper a modified topology for symmetrical and asymmetrical configuration of MLI is proposed for increased output voltage levels with reduced number of semiconductor switches. A comprehensive study of proposed configuration of MLI is carried out in terms of switch counts and blocking voltage. The detailed simulation study of the proposed concept has been carried out using MATLAB/SIMULINK and validated experimentally.