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The authors examine efficient parameter extraction and accurate modeling for submicrometer transistors. Topics include small-signal equivalent circuits, saturation regions, and gate resistance.

A compact neural network algorithm for partial-response maximum-likelihood (PRML) sequence detection is presented. Compact neural networks are a class of locally connected neural networks suitable for very large scale integration (VLSI) implementation. The hardware complexity for VLSI implementation of the proposed algorithm grows linearly with the level of the deliberately designed symbol interference effects of the partial-response (PR) signaling scheme. Large dedicated memory for storage of likelihood matrices in digital Viterbi-algorithm-based detectors is not needed for the proposed detector. Detailed analysis on network stability for network topology and time constant of an analog neuron is described. This detector algorithm has competitive bit-error rate performance when compared with the digital Viterbi algorithm under the noise condition for many real-world applications. The proposed algorithm is suitable for analog VLSI implementation because of its low time complexity and linear area complexity for the detection of PRML signaling schemes. Index Terms - Communication, distributed parallel processing, maximum-likelihood sequence estimation, neural networks, partial response.

Very large scale integration (VLSI) compact neural network architecture for maximum-likelihood detector of partial response (PR) communication receivers is presented. The compact neural network approach has many attractive advantages in achieving low power, low cost, compact chip area, and faster processing speed by its loosely coupled parallel processing nature. In this paper, the design of a state-constrained analog neural processor, and the corresponding parallel architecture to realize the PR detection algorithms and the related scalability and performance evaluation issues are described with detailed design analysis. A design example of PR IV detector have been used to demonstrate the advantages of such a scalable massive VLSI architecture. A processing rate of 265 Mb/s was achieved with SPICE simulation for a prototype PR IV detector on a silicon area of 5.14 mm x 5.81 mm in a 1.2-[[micro]meter] CMOS technology. An estimated processing capacity of 886 Mb/s can be achieved if the same design is scaled up to a 1.0-[cm.sup.2] silicon area for the same technology. Such promising performance potential clearly indicates that VLSI compact neural network detector can meet the needs in future high speed data communication systems at very low cost. Index Terms - Neural network, mixed-signal, parallel processing, partial response, scalable design, VLSI.

A compact neural-network receiver for code-division multiple-access (CDMA) communication is presented. In the CDMA scheme, the near-far problem is a major impediment for the performance of a conventional detector (CD). By using a compact neural network with hardware annealing function and gradient-descent optimization technique, an optimal multiuser receiver can be implemented. The algorithm and simulation results of the compact neural-network-based CDMA receiver are described in this brief. Index Terms - Optimization, multimedia, neural network, receiver, spread spectrum, wireless communication.

Rapid progresses in computers, telecommunication, and consumer electronics research have stimulated the emergence of powerful multimedia systems that will have profound impacts on scientific, industrial, business endeavors, and even our daily lives. Continuous advances in deep-submicron microelectronic fabrication technologies have made possible the integration of millions of transistors on a single silicon microchip. However, one of the anticipated major technological breakthroughs will be the efficient and reliable use of optical links to increase the communication bandwidth and quality of electronic systems. Optical links can be used not only at the machine-to-machine level, but also at the board-to-board and chip-to-chip levels. The architecture, design, and associated measurement results are presented regarding the use of optical interconnections to enhance desktop multimedia computing systems. Index Terms - Computer graphics, multimedia, multiprocessing, optical interconnection, parallel processing.