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This paper designs two single-stage LC-tank injection-locked frequency sixtuplers (ILFSs) fabricated in a 90 nm CMOS process and it describes the circuit design, operation principle, and measurement results of the ILFSs. The ILFS circuit with a differential input and single-phase output is made of a first-harmonic injection-locked oscillator (ILO), a frequency tripler, and a push-push doubler. The first ILFS uses an octagonal inductor. For a supply voltage of 0.4 V, the free-running frequency is around 41.52 GHz, DC power consumption is 9.03 mW at the incident power of 0 dBm, and the output locking range at 0 dBm input power is 10.21 %. The second ILFS uses an 8-shaped inductor for low electromagnetic (EM) noise generation. The free-running frequency is around 37.2 GHz, DC power consumption is 7.72 mW at the incident power of 0 dBm, and the output locking range at 0 dBm input power is 17.4 %. The two chips have the same area, $0.7\times0.7$ mm2. This paper also provides a further analysis and comparison of the RF performance of on-chip inductors designed. Simulation shows the substrate noise coupling and distance noise coupling between victim and aggressor, the 8-shaped inductor exhibits a significant reduction in coupling. By the measurement results, it is evident that the performance of the 8-shaped inductor ILFS is superior to that of the octagonal inductor ILFS.

This paper designs a C-band single-stage $LC$ -tank injection locked frequency quintupler (ILFQ) fabricated in $0.18~\mu \text{m}$ CMOS process. The differential input/output ILFQ circuit is made of a first-harmonic injection-locked frequency oscillator (ILO) and a frequency quadrupler/quintupler. The free-running oscillation frequency of the ILFQ is around 7.6 GHz. At the dc power consumption of 9.9 mW and at the incident power of 0 dBm, the input locking range is from the incident frequency 1.456 GHz to 1.644 GHz to provide an output signal source from the frequency 7.28 GHz to 8.22 GHz. The whole chip occupies a die area of $1.114\times 1.060$ mm2. The designed circuit is also used as a new X-band single-stage LC-tank injection locked frequency quadrupler, which shows measured $\times 4$ output locking range from 7.82 GHz to 8.6 GHz.

High multiplication-factor even-modulus frequency multipliers are often configured as multi series frequency multipliers. This paper designs a single-stage $LC$ -tank injection locked frequency sixtupler (ILFS) fabricated in $0.18~\mu \text{m}$ CMOS process and the ILFS merges many sub-circuits in one by sharing a common supply and passive inductive elements. The circuit design, operation principle and measurement results of the ILFS are addressed. The differential input and single-phase output ILFS circuit is made of two frequency doublers, a first-harmonic injection-locked oscillator and an active frequency tripler using one frequency doubler. The free-running oscillation frequency of the ILO is around 5.716 GHz. At the dc power consumption of 20.9 mW and at the incident power of 0 dBm, the $\times 6$ input locking range is from the incident frequency 0.94 GHz to 1.02 GHz to provide an output signal source from the frequency 5.64 GHz to 6.12 GHz. The whole chip occupies a die area of $1.141\times 1.2$ mm2. Other high multiplier factors are also measured on the designed chip.

This paper proposes and analyzes a CMOS divide-by-8 injection locked frequency divider (ILFD) with a divide-by-2 ring oscillator stacked on a capacitive cross-coupled oscillator used as an LC divide-by-4 ILFD. The divide-by-8 ILFD in the TSMC $0.18~\mu \text{m}$ 1P6M CMOS process has a locking range from 15.5 GHz to 17.8 GHz at the power consumption of 10 mW. The varactorless divide-by-8 ILFD occupies a small area of $0.8044\times 0.72$ mm2. The ILFD can be used in divide-by-4 mode and has a locking range from 4.8 GHz to 10.6 GHz at the power consumption of 10.43 mW. The ring oscillator based frequency divider (FD) is designed with a pair of differential outputs so that the whole divide-by-8 ILFD provides differential output. The ring oscillator FD uses unbalanced component parameters to optimize the circuit performance and it supplies two unbalanced tail currents to the LC ILFD, which also provide unbalanced outputs despite the circuit topology is a symmetric one. The unbalanced approach offers design flexibility.

This article describes two low-power and wide locking range capacitive cross-coupled divideby-2 injection-locked frequency dividers (ILFDs) implemented in TSMC standard 0.18 μm processes. The ILFDs are based on a differential VCO with one direct injection MOSFET for coupling the external signal to the spiral-inductor resonator. The first/second ILFD uses five/three on-chip inductors in series with parasitic varactors as a multi-resonance resonator. Three measured features are identified. The ILFDs have two non-overlapped locking ranges at low input power, they have two free-running oscillation frequency bands, and the frequency tuning versus gate bias of cross-coupled transistors shows the frequency tuning hysteresis. The power consumption of the 5-L ILFD core is 5.43 mW and the locking range is 6.07 GHz (116.395%) from 2.18 to 8.25 GHz at injection power Pinj =0 dBm. At the supply voltage of 1.1 V, the divider's free-running oscillation frequency is 3.13 GHz. The die area of the 2nd chip is 0.865 × 0.872 mm2. The locking range at low input power is larger for the 5-L resonator ILFD.