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Molybdenum disulfide (MoS2), a typical member of the transition metal dichalcogenides (TMDs) group, is known for its excellent electronic performance and is considered a candidate next-generation semiconductor. The preparation of MoS2 nanoflakes for use as the core of semiconducting devices depends on mechanical exfoliation, but its quality has not yet been optimized. In this paper, a novel exfoliation method of achieving MoS2 nanoflakes is proposed. We find that the size and yield of the exfoliated flakes are improved after thermal treatment for 2 h at a temperature of 110°C followed by precooling for 10 min in ambient air. The new method has the advantage of a 152-fold larger size of obtained MoS2 flakes than traditional mechanical exfoliation. This phenomenon may be attributable to the differences in van Der Waals force and the increase in surface free energy at the interface induced by thermal treatment. In addition, a field-effect transistor (FET) was fabricated on the basis of multilayer MoS2 prepared according to a new process, and the device exhibited a typical depleted-FET performance, with an on/off ratio of ~105 and a field-effect mobility of 24.26 cm2/Vs in the saturated region when VG is 10 V, which is generally consistent with the values for devices reported previously. This implies that the new process may have potential for the standard preparation of MoS2 and even other 2D materials as well.

Molybdenum disulfide (MoS2) field-effect transistors (FETs) with four different metallic electrodes (Au,Ag,Al,Cu) of drain-source were fabricated by mechanical exfoliation and vacuum evaporation methods. The mobilities of the devices were (Au) 21.01, (Ag) 23.15, (Al) 5.35 and (Cu) 40.52 cm2/Vs, respectively. Unpredictably, the on-state currents of four devices were of the same order of magnitude with no obvious difference. For clarifying this phenomenon, we calculated the Schottky barrier height (SBH) of the four metal–semiconductor contacts by thermionic emission theory and confirmed the existence of Fermi-level pinning (FLP). We suppose the FLP may be caused by surface states of the semiconductor produced from crystal defects.