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Objectives To explore the feasibility of preoperative prediction of vascular invasion (VI) in breast cancer patients using nomogram based on multiparametric MRI and pathological reports. Methods We retrospectively collected 200 patients with confirmed breast cancer between January 2016 and January 2018. All patients underwent MRI examinations before the surgery. VI was identified by postoperative pathology. The 200 patients were randomly divided into training (n = 100) and validation datasets (n = 100) at a ratio of 1:1. Least absolute shrinkage and selection operator (LASSO) regression was used to select predictors most associated with VI of breast cancer. A nomogram was constructed to calculate the area under the curve (AUC) of receiver operating characteristics, sensitivity, specificity, accuracy, positive prediction value (PPV) and negative prediction value (NPV). We bootstrapped the data for 2000 times without setting the random seed to obtain corrected results. Results VI was observed in 79 patients (39.5%). LASSO selected 10 predictors associated with VI. In the training dataset, the AUC for nomogram was 0.94 (95% confidence interval [CI]: 0.89–0.99, the sensitivity was 78.9% (95%CI: 72.4%–89.1%), the specificity was 95.3% (95%CI: 89.1%–100.0%), the accuracy was 86.0% (95%CI: 82.0%–92.0%), the PPV was 95.7% (95%CI: 90.0%–100.0%), and the NPV was 77.4% (95%CI: 67.8%–87.0%). In the validation dataset, the AUC for nomogram was 0.89 (95%CI: 0.83–0.95), the sensitivity was 70.3% (95%CI: 60.7%–79.2%), the specificity was 88.9% (95%CI: 80.0%–97.1%), the accuracy was 77.0% (95%CI: 70.0%–83.0%), the PPV was 91.8% (95%CI: 85.3%–98.0%), and the NPV was 62.7% (95%CI: 51.7%–74.0%). The nomogram calibration curve shows good agreement between the predicted probability and the actual probability. Conclusion The proposed nomogram could be used to predict VI in breast cancer patients, which was helpful for clinical decision-making.

This study aimed to validate the safety and effectiveness of percutaneous doxycycline/albumin injection for spinal aneurysmal bone cysts (ABCs) as an alternative to open surgery. From January 2000 to December 2016, 25 patients who had no/minor neurological deficits (modified Frankel scale D or E) and acceptable local stability (spinal instability neoplastic score

Most of the risk models for predicting contrast-induced acute kidney injury (CI-AKI) are available for postcontrast exposure prediction, thus have limited values in practice. We aimed to develop a novel nomogram based on preprocedural features for early prediction of CI-AKI in patients after coronary angiography (CAG) or percutaneous coronary intervention (PCI). A total of 245 patients were retrospectively reviewed from January 2015 to January 2017. Least absolute shrinkage and selection operator (Lasso) regression model was applied to select most strong predictors for CI-AKI. The CI-AKI risk score was calculated for each patient as a linear combination of selected predictors that were weighted by their respective coefficients. The discrimination of nomogram was assessed by C-statistic. The occurrence of CI-AKI was 13.9% (34 out of 245). We identified ten predictors including sex, diabetes mellitus, lactate dehydrogenase level, C-reactive protein, years since drinking, chronic kidney disease (CKD), stage of CKD, stroke, acute myocardial infarction, and systolic blood pressure. The CI-AKI prediction nomogram obtained good discrimination (C-statistic, 0.718, 95%CI: 0.637-0.800, p = 7.23 × 10-5). The cutoff value of CI-AKI risk score was -1.953. Accordingly, the novel nomogram we developed is a simple and accurate tool for preprocedural prediction of CI-AKI in patients undergoing CAG or PCI.

Background A key challenge in thyroid carcinoma is preoperatively diagnosing malignant thyroid nodules. The purpose of this study was to compare the classification performance of linear and nonlinear machine-learning algorithms for the evaluation of thyroid nodules using pathological reports as reference standard. Methods Ethical approval was obtained for this retrospective analysis, and the informed consent requirement was waived. A total of 1179 thyroid nodules (training cohort, n = 700; validation cohort, n = 479) were confirmed by pathological reports or fine-needle aspiration (FNA) biopsy. The following ultrasonography (US) featu res were measured for each nodule: size (maximum diameter), margins, shape, aspect ratio, capsule, hypoechoic halo, composition, echogenicity, calcification pattern, vascularity, and cervical lymph node status. We analyzed five nonlinear and three linear machine-learning algorithms. The diagnostic performance of each algorithm was compared by using the area under the curve (AUC) of the receiver operating characteristic curve. We repeated this process 1000 times to obtain the mean AUC and 95% confidence interval (CI). Results Overall, nonlinear machine-learning algorithms demonstrated similar AUCs compared with linear algorithms. The Random Forest and Kernel Support Vector Machines algorithms achieved slightly greater AUCs in the validation cohort (0.954, 95% CI: 0.939–0.969; 0.954 95%CI: 0.939–0.969, respectively) than other algorithms. Conclusions Overall, nonlinear machine-learning algorithms share similar performance compared with linear algorithms for the evaluation the malignancy risk of thyroid nodules.

The aim of this study was to develop an ultrasound-based nomogram to improve the diagnostic accuracy of the identification of malignant thyroid nodules. A total of 1675 histologically proven thyroid nodules (1169 benign, 506 malignant) were included in this study. The nodules were grouped into the training dataset (n = 700), internal validation dataset (n = 479), or external validation dataset (n = 496). The grayscale ultrasound features included the nodule size, shape, aspect ratio, echogenicity, margins, and calcification pattern. We applied least absolute shrinkage and selection operator (lasso) regression to select the strongest features for the nomogram. Nomogram discrimination (area under the receiver operating characteristic curve, AUC) and calibration were assessed. The nomogram was subjected to bootstrapping validation (1000 bootstrap resamples) to calculate a mean AUC and 95% confidence interval (CI). The nomogram showed good discrimination in the training dataset, with an AUC of 0.936 (95% CI: 0.918–0.953) and good calibration. Application of the nomogram to the internal validation dataset also resulted in good discrimination (AUC: 0.935; 95% CI, 0.915–0.954) and good calibration. The model tested in an external validation dataset demonstrated a lower AUC of 0.782 (95% CI: 0.776–0.789). This ultrasound-based nomogram can be used to quantify the probability of malignant thyroid nodules. • Ultrasound examination is helpful in the differential diagnosis of malignant and benign thyroid nodules. • However, ultrasound accuracy relies heavily on examiner experience. • A less subjective diagnostic model is desired, and the developed nomogram for thyroid nodules showed good discrimination and good calibration.

High performance power device is necessary for BCD power device. In this paper, we used 3D Synopsis TCAD simulation tool Sentaurus to develop 120V device and successfully simulated. We implemented in a conventional 0.35um BCDMOS process to present of a novel high side 120V LDMOS have reduced surface field (RESURF) and Liner p-top structure with side isolation technology. The device has been research to achieve a benchmark specific on-resistance of 189 mΩ-mm2 while maintaining horizontal breakdown voltage and vertical isolation voltage both to target breakdown voltage of 120V. In ESOA, we also proposed a better performance of both device without kirk effect.

In this paper, we report nanowire drain saturation current sensitivity property to measure femtomol level change in drain current due to different proteins i.e. DNA with numerical simulation and fabricated polysilicon nanowire based on the theoretical predictions. In addition, the drain current will also be affected by the back-gate voltage and will increase as the back-gate voltage increases. A 3-dimensional Synopsis tool is used to investigate the drain current behavior for a polysilicon nanowire. The scattering compact model reported result of detailed numerical calculation shows in good agreement, indicating the usefulness of scattering compact model. Whereas 3D synopsis unable to explain the whole region of the drain current characteristics in linear region which uses quantum mechanics model approach.

In VDMOS device the anti-JFET concentration has important role for determining the breakdown voltage and on-resistance of the device. Because higher N-drift doping concentration can provide the very best on-resistance of the device but also decrease breakdown voltage. It also has a proportional relationship with threshold voltage degradation. In this paper, we report the anti-JFET implantation energy influence effect electric potential distribution, the highest impact ionization shifted from the silicon surface to deeper. It will have less hot carrier impact, and we have found higher breakdown voltage. The anti-JEFT implantation is critical for on-resistance off-state breakdown voltage optimization, However the high field and high impact ionization near the gate region will cause severe hot carrier Injection problem. The general expectation of high voltage VDMOS transistor is to have higher breakdown voltage, less degradation due to hot carrier injection and better on-resistance.

In this paper, a novel 120V multiple RESURF lateral double-diffused MOS (LDMOS) transistor with shallow trench isolation (STI) structure in low side is developed and successfully simulated. The proposed multiple RESURF LDMOS is able to achieve better ESOA performance while maintaining a benchmark specific on-resistance with breakdown voltage over 120 Volts. The key feature of this novel device is linear p-top rings which are located in the n-drift region. Optimization of p-top mask design and n-drift region concentration is performed in order to achieve the lowest on-resistance possible with the desired breakdown voltage.

This paper presents how to improve specific o n-state resistance (Ron) induced by the HCI of a SOI LDMOS device. In manufacturing of UHV device, trade-off between on state resistance and breakdown voltage is always present. But with our process design we are able to improve Ron degradation without compromising the-breakdown voltage. In our design the peak electric field is under gate near source side, due to low electric field near drain helps to increase the current flow much better hence it helps to improve Ron and Vth. If the peak field is located near drain side, the hot holes is easy to penetrate to field oxide and avoid current flow then it causes increase in the Ron.Our simulation results shows 0.27% and 0.95% Ron and Vth increases respectively even at 1e5 second stress time .The Ron degradation phenomenon was analyzed with the 2-D simulation of electric field and impact ionization generation.

For IC component designs, ESD is one of an important issue which has to be taken in consideration for reliability of a device. We use the TLP Voltage Stepping simulation scheme in Medici simulation for 5V NMOS Multi-finger structure, the use of silicon model and set of variables, in silicon material parameter is used to vary the variable electron and hole parameters of silicon, which can make the Holding Voltage simulation change and to make the simulation and the silicon data more consistent. We have simulated and calibrated Holding voltage of 5V NMOS multi finger to match with silicon data.

Ion implantation and subsequent diffusion are very essential stages in today's advanced VLSI (Very Large Scale Integration) semiconductor devices processing. High precision calibration of device simulation is a key procedure to ensure simulation is accurate. For this purpose, accurate prediction of the doping profiles resulted from ion implantation and diffusion will be studied using a few models of ion implantation and diffusion. We collected data of Boron as P-type ion implantation profiles using TCAD simulation software with different ion implantation models and diffusion models then compared with Secondary Ion Mass Spectrometry (SIMS) data of ion implantation profile database as experimental data. Models plays very important role in this calibration. In this paper, calibrations have done using Monte Carlo and Taurus analytical as implantation model and pd.full, pd.fermi and pd.5stream as diffusion model. All calibration simulations were simulated using Synopsys TCAD Simulation. The experimental results shown by using Monte Carlo ion implantation model with pd.5str diffusion model is close to SIMS profile.

Unclamped Inductive Switching (UIS) is a very high stress test used for characterizing the ruggedness in terms of the maximum avalanche energy can be handled by the device. Optimizing the design for better reliability and ruggedness of power MOSFET was studied. In this paper, we investigated effects of current density and hotspot temperature distribution during unclamped inductive switching (UIS) test for P-channel LDMOSFET. It is shown that the simulation results are found to be in good correlation between the maximum avalanche energy handling capability and identification of the mechanism of device-failure (current density distribution effects and hotspot temperature location). Uniformity of current density in each finger of the device can help to improve the maximum avalanche energy handling capability. If current density distribution and temperature hotspot region effects can be suppressed more uniform in each finger of the critical regions, the device is expected to sustain higher avalanche energy during stress.

To increase typically low output drive currents from Si Nanowire field-effect transistors (FETs), we show a GaN based GAA Nanowire FET’s effectiveness. The theoretical study is focused on the three dimensional device designs, comparisons, random dopant fluctuation using IFM, and general variability issues including nanowire length, gate work function, and channel thickness are discussed. Performance of GaN GAA Nanowire is found to be increasing as Gate length is increased. Electrical characteristics of FETs including threshold voltage saturation, On/Off current ratio and sub threshold slope (SS) are analyzed. GaN GAA structure let to gate control ability improvement compared to Si based Nanowire in electrical performance. The GaN GAA Nanowire subthreshold slope is ~62mV/decade, which is close to the theoretical limit 60 mV/decade and leads to very high Ion/Ioff ratio of 1010-1011. The GaN GAA Nanowire is a very promising candidate for high-performance.

In this paper, a low-cost 900V rated multiple RESURF lateral double-diffused MOS (LDMOS) transistor in junction-isolated power IC technology without EPI layer is developed and successfully simulated. Don't think that the bigger the processing node the lower the cost. There are LDMOS processes today at the 0.35-micron node that use the same number of masks that are required at the 1.0-micron node. Moreover, smaller processing nodes yield smaller chip sizes, which carry both performance and cost benefits. Evaluate EPI vs. non-EPI wafers, and if your performance requirements can be met with non-EPI that is the best choice for lower cost implementation. Detailed device simulations and structure designs have been done. The optimized devices show excellent performance, which have been demonstrated with characterization results from device. The proposed multiple RESURF LDMOS without EPI Layer is able to achieve a specific on-resistance of lower than 250 mΩ-cm2 while maintaining a breakdown of over 900 volts.

Improvement of Laterally Diffused Metal Oxide Semiconductor (LDMOS) energy capability, Unclamped inductive switching (UIS) is used to characterize ruggedness in terms of the maximum avalanche energy that device can handle prior to destructive breakdown. Maximum amount of UIS energy (E AS ) sustained by device before failure is evaluated and have linear relationship with number of device finger and device-width. As we know that in multi-finger LDMOS the equivalent parasitic resistance gets lowered and MOS cells hence avoiding possibility of current failure. With lowered parasitic resistance Maximum energy of avalanche in single pulse (E AS ) energy increases linearly with number of fingers.[l]

In this paper, a normal nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type poly-silicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride buried oxide nanowire realizes drain saturation current (Ids) sensor to compensate device variation.

Electrostatic Discharge (ESD) has become one of the most critical reliability issues in integrated circuits (ICs). The number of circuit design iteration due to electrostatic discharge (ESD) failures increases with the complexity of VLSI technologies and their shrinking. In this paper, we show how TCAD simulation and ESD macro-model can be used to solve ESD protection issues in GGNMOS (Gate-Grounded NMOS) technology. A macro-model for ESD circuit simulation with only fitting parameter proposed. This system of model equations can capture most of the physical phenomena of the heat generation and conduction inside nano-scale devices with moderate numerical complexity. It is anticipated that the modeling concepts developed in this research may be applied in future ESD simulation studies.

Extreme learning machine (ELM) is a fast online learning algorithm for single hidden layer feed-forward neural networks (SLFN), which keeps the fast learning speed with good performance. And it has been widely used on function approximation and prediction classification. However, the parameters in hidden layer of ELM are randomly determined which leads to the unstable prediction performance. So the ELM weighted hybrid modeling method is proposed. Firstly, several ELM sub-models of high precision are trained and stored in the model base. When a new sample needs to be predicted, those ELM sub-models are combined with weight as the hybrid model to output the prediction result. The hybrid model reduces the randomness of prediction with single ELM, and improves the accuracy and ensures the relative stability of the prediction results. Due to the time-varying in process, the model modification conditions and sliding window sample length are set. And the sub-models in model base which prediction error exceeds the threshold will be retrained online, so as to modify the hybrid model online. Four simulation examples verify the effectiveness of the proposed method.

A new double integration-based method to extract model parameters is applied to experimental polysilicon nanowire MOSFETs. It was experimentally found that the saturation current shows the sensitivity of the Nano-wire MOSFETs if the conventional method fails to show the sensitivity depending upon the threshold voltage of Nano-wire MOSFET. It shows that the present method offers advantage over previous extraction procedure which use trans-conductance curve in the saturation mode, and the threshold voltage is determined by the intercept of curve. In addition to show how compact model for the I d -V g characteristics are numerically evaluated and examined. The drain and gate bias dependencies of device current are shown. Also the model we proposed fits to the silicon data. Our experimental results support the model which we proposed in this paper. The drain current measured in saturation region can easily show the change in current level at different conditions but the convention theory for the linear region is difficult to do for sensitivity test of Nano-wire.

The growth rate of epitaxy depends primarily on parameters such as source gas deposition temperature pressure and concentration. Most microelectronic circuits fabrication that use epitaxial wafers require a lightly epitaxial layer (1014–1017 atom/cm3) on a heavily doped substrate (1019–1021 atom/cm3). The distribution of vacancies and interstitials is important for the distribution of the high surface concentration enhancement of tail diffusivity and oxidation enhanced diffusion. We present the auto doping during the epitaxy growth process which is being ignored most of the time during the device fabrication. Also the defects which are formed during the growth of epitaxy. The present simulation solves for the transient interstitials distribution assuming that interstitials are at equilibrium with vacancies.

The soft sensor models constructed based on historical data have poor generalization due to the characters of strong non-linearity and time-varying dynamics. Moving window and recursively sample updating online modeling methods can not achieve a balance between accuracy and training speed. Aiming at these problems, a novel online learning neural network LNN selects high-quality samples with just-in-time learning JITL for modeling. And the local samples could be further determined by principal component analysis PCA. The LNN model shows better performance but poor stability. Weighted multiple sub models, the hybrid model improves accuracy by covering deficiencies. Additionally, the weights could be developed with mean square error MSE of each sub model. And the detailed simulation results verify the superiority of adaptive weighted hybrid model.

This work demonstrates the effect of fingers, device-width and inductance on reverse recovery of LDMOS by unclamped inductive switching (UIS) circuit simulation for two dimensional (2D) and three dimensional (3D) devices. All the observations have been done for maximum pulse width at which device pass under UIS test. For UIS simulations the failure criteria is taken as the device temperature reaching a critical value of 650K. It has been shown that reverse recovery charge (Qrr) increased linearly with number of fingers, device width and inductance.

In this paper, the effect of poly-gate extension on improved ruggedness of n-type LDMOS is evaluated by two-dimensional (2D) device and circuit simulation. Multi-finger dimension of n-type LDMOS is subjected to Unclamped Inductive Switching (UIS) stress test to determine its ruggedness. It is shown that the poly-gate extended device yields approximately 15% higher avalanche energy handling capability (Emax) as compared to that without extended poly-gate region. This work suggests that the improvement in ruggedness of the optimized design is attributed to the suppression and shift of the electric field peaks away from the critical regions. The results from simulation are found to be in good correlation with experimental UIS test results in terms of avalanche energy range, identification of the mechanism of device-failure and hot-spot location. It is believed from the results obtained that this approach will have remarkable impact in the ruggedness if implemented for large-array devices (LAD).

This work demonstrates the effect of increasing finger number and width on the ruggedness of the nLDMOS device under test (DUT). The ruggedness or energy handling capability is analyzed by two-dimensional (2-D) and three dimensional (3-D) device and circuit simulations. The set failure criterion in our study and simulation is the device temperature reaching a critical value equal to the melting point of metal-contacts. The maximum energy is calculated by considering the pass-case prior to device failure and time-integrating the drain voltage and current for the avalanche duration. Maximum avalanche energy handling capability is seen to be increased linearly with number of device fingers. UIS test was also performed on width extended multi-finger nLDMOS device structures. The simulated results provided useful approaches to predict real experimental results and contribute to their physical interpretation by identification of the mechanism of device-failure, hot-spot location and continuous temperature extraction.

The effect of negative, neutral and positive stress by Si3N4 film on AlGaN layer of AlGaN/GaN based high electron mobility transistor (HEMT) heterostructure has been investigated by varying different stress values using Synopsys Sentaurus device simulation. This paper shows a relation between the stresses of passivation layer, two dimensional electron gas (2DEG) formed at the interface of AlGaN/GaN region and respective drain current. The increase in negative stress will result in the increase of 2DEG density, which will result in the increase of drain current. Additionally, the 2DEG density was found to be depended on the applied bias voltage, showing the higher drain sweep voltage will increase the 2DEG density. This study also provides the effect of stress on direct-current (DC) capacitance-voltage characteristics of device electrical performance. It suggests that the capacitance will be increased with the increasing positive stress, indicating the change in interface states due to stress effect.

A new compatibilizer with polypropylene as matrix, Glyceryl monostearate (GMS) and styrene(St) as functional group was prepared, and its effect on the properties of polypropylene(PP)/montmorillonite(MMT) nanocomposites was investigated. Fourier transform infrared spectroscopy results showed that the GMS and St monomers had successfully been grafted on the backbone of PP. The characterization results of X-ray diffraction(XRD) pointed out the crystallite size perpendicular to the crystal plane in PP/ compatibilizer / MMT nanocomposites was smaller than that of PP. Through detecting of transmission electron microscope(TEM), it can be found that the new compatibilizer will improve the dispersibility of MMT in PP matrix. At last, the mechanic properties of PP/MMT nanocomposite materials get determination, the mechanical strength especially impact strength had a obvious progress when O-MMT was added, and its maximal value impact strength appears in the 3% montmorillonite and 20% compatibilizer.

This paper reports a novel device structure which operates at low electrical field and high potential at internal drain point .The kink and quasi-saturation effects were minimized for this small 0.15 micron SOI LDNMOS with 0.13 micron gate length. Numerical simulation is used to show that the potential and electric field distribution within a small linear thickness (LT) LDMOS SOI device is quite different from that observed lateral linear doping (LD), uniform and vertical linear doping (VLD) devices. Reduction of drain electric field and of inter drain point potential barrier brings about a dramatic decrease of Kink effect improvement of quasi-saturation, large safe operate area (SOA) performance and lower on-resistance (Ron).

Lateral DMOS power devices can achieve high breakdown voltage by optimizing the two dimensional (2-D) device parameters in accordance with the RESURF principle. However, in practice, it is also necessary to optimize the three dimensional (3-D) device parameters in order to support a given breakdown voltage. In this paper, We report the effect of 3-D parameters such as the curvatures of the drain and source regions, doping density of LDMOS device with SOI (Silicon-On-Insulator) substrates based on numerical simulations and analytical solutions using cylindrical coordinates with device simulator "MEDICI" and Synopsys 3D simulator Sentaurus 2009.06-SP2 version. We stress the necessary 3D simulation for power device with racetrack, interdigitated layouts etc.

A variety of lateral high-voltage devices has been investigated in the range of 200V to 300V applications in power ICs, including reduced surface electric field (RESURF), laterally double diffused MOS (LDMOS) transistor, lateral variation doping (LVD), vertical linear doping (VD) and linear thickness (LT) devices. These devices are described and compared on the basis of on-state, off-state breakdown voltages, on-state resistance (Rdson), safe operation area (SOA) and Baliga's Figure-Of-Merits (BFOM). It is observed that for devices operating lesser than 300V, the VD LDMOS exhibits superior performance, where as higher voltage devices (≧300 V), the LT device proves to be superior. Applications arround 200 V, the VD device exhibits only a marginal improvement over the LT LDMOS device.

The high junction leakages, circuit latched issues, and high parasite capacitances happened in junction isolation technology can be improved by the thin SOI (Silicon-On-Insulator) technology. A CMOS compatible SOI technology will be one of technologies used in the future roadmap of LDMOS devices. A CMOS compatible thin SOI LDMOS (Lateral Double-diffused MOSFET) device, with 0.18 micron gate length, 0.02 micron gate oxide and 3 micron N-drift region, is proposed to achieve the optimal (BVoff) off-state breakdown voltage and on-state resistance (Ron) values. The characteristics of the proposed LDMOS device are verified by the two-dimensional process simulator TSuprem-IV and the device simulator Medici. The simulated results have shown that a device performance at the range of BVoff, 80 v, and Ron, 190 mohm-mm2, is attended. The on-state breakdown voltage is measured at 70V with an excellent safe operating area (SOA) performance for the drain source current versus on-state breakdown voltage.

In this study, we demonstrated the characteristics of nonvolatile silicon oxide nitride oxide silicon (SONOS)-type memories using cerium oxide (CeO2) nanocrystals as a charge storage agent. We observed that the shape of the formed CeO2 nanocrystals is nearly spherical and that their size is almost similar identical to their high density of 5×1011 cm-2. Such CeO2 nanocrystals were formed by depositing a thin CeO2 film of ca. 2–3 nm thickness using an evaporater gun system and then rapid thermal annealing (RTA) in O2 ambient at 900 °C for 1 min. The fabricated memory devices show good electrical properties in terms of a sufficiently large memory window (>2 V), program/erase (P/E) speed (0.1/1 ms), retention time up to 104 s with only 5% charge loss, and endurance after 105 cycles with small memory window narrowing and two-bit operation. These properties suggest that the nonvolatile SONOS-type memories with the CeO2 nanocrystal trapping agent can be applied in future flash memories.

In Complementary Metal Oxide Semiconductor (CMOS) process, isolation is the key and it has got more influence on the device performance. The most advanced process is using Shallow trench isolation (STI) technology, but for small geometry processes using STI technology will be very difficult because of severe HCI (Hot Carrier Injection) problem and need to have new advanced equipment for using STI technology. So many factories still using Local Oxidation of Silicon (LOCOS) isolation for small geometry applications like nano-devices. LOCOS isolation has a problem because of its bird's beak will occupy big area and causes leakage path. Using Poly-Buffer in the LOCOS isolation will reduce the bird's beak around 40% and hence CMOS integration process improves product yield and performance will be drastically improved. Feature of the model using Poly-Buffered LOCOS (PBLOCOS) is very similar and very easy than using basic LOCOS process. Sometime PBLOCOS Isolation will be more useable than STI technology.

This work investigates the degradation of electrical characteristics of amorphous silicon thin-film transistors during the accelerated ESD stress with a 40V high voltage and a high/low current of 2 mA/0.1 μA conditions. Both the leakage current and the threshold voltage shift are severe as the accelerated ESD stress applied at the gate region. The 40V accelerated ESD stress with a high current has more severe impact on the electrical performance of device than that with a low current.

This paper investigates a relatively new photoresist MR-I 7010R for its use in thermal nanoimprint lithography. The primary aspects tested were the thickness of the photoresist post imprinting and uniformity of the resulting residual layer thickness (RLT). These aspects were determined with respect to the initial thickness of the photoresist, which was deposited via spin-on coating, and change in pressure. Uniformity of the RLT is critical to the effectiveness of the resist's use in thermal nanoimprint lithography as it determines the efficiency at which it can be etched. Imprinting with several conditions has been achieved with well acceptable residual layer to keep the stamp lifetime and efficiency of etching process.

Nano-imprinting technology, as one of the most promising fabrication technologies, has been demonstrated to be a powerful tool for large-area replication up to wafer-level, with features down to nanometer scale. This study aims to develop capabilities in patterning nano structure using thermal nano-imprint lithography (NIL). 30nm Si molds are patterned by electron-beam lithography (EBL) using NEB22 A2 negative e-beam resist. The NEB22 A2 negative e-beam resist possess a variety of characteristics desirable for NIL, such as low viscosity, low bulk-volumetric shrinkage, high Young's modulus, high thermal stability, and excellent dry-etch resistance. The excellent oxygenetch resistance of the barrier material enables a final transfer pattern that is about three times higher than that of the original NIL mold. Based on these imprint on negative electron beam resist approach is used for pattern transfer into silicon substrates. The result is a high-resolution pattern with feature sizes in the range of nanometer to several microns.

In this paper an Hspice macro model is presented to model the snapback characteristics of GGNMOS (gate-grounded NMOS) and GCNMOS (gate-coupled NMOS) under ESD stress. The 5V NMOS be simulated in this paper is based on the 0.35um BCD technology as an ESD protection device. The new macro model has successfully predicted the trigger voltage and holding voltage of the GGNMOS and GCNMOS according to the silicon data. The effects of device parameters Tref and Rs exhibit a good trend curve in agreement with BJT model, which helps for the prediction of the trigger voltage and holding voltage for ESD circuit application.

In this paper, we present high voltage NLDMOS structure with multiple RSEURF concepts. The NLDMOS is based on 0.35µm BCD process. The multiple RESURF device base on charge balance theory using P-top and N-top to achieve high breakdown voltage and low on-resistance. The 2D simulation result compares the conventional single RESURF NLDMOS structure and the new structure with multiple RESURF devices. The new device concept help to improve the on-resistance up to 20% were as keeping the breakdown voltage still in the acceptable range for 40V rated device. The 2D simulation is using by process simulator Tsuprem4 and Medici to verify the device concept and identify the electrical characteristics.

This work presents a design guideline for free latch-up in the CMOS inverter caused by shifting time waveform for various device sizes which is demonstrated by 2D TCAD simulations. The design window for improving the CMOS latch-up is investigated by increasing distance anode to cathode of parasitic silicon-controlled-rectifier (SCR) or source to bulk of NMOS.

Threshold voltage shift is a major problem for UMOS device. This study explains how device performance can be affected by silicon defects (interstitial and Vacancy). Interstitial may be induced by epitaxy process or trench process. Interstitial enhances the dopant diffusion. In TCAD simulation interstitial distribution is different for different diffusion model and shows shift in the threshold voltage for different interstitial distribution.

In this work, high voltage NLDMOS performance in terms of high blocking voltage and On-Resistance have been investigated. In order to obtain the optimum electrical performance several key factors have been optimized such as linearity of HVNW profile, drift length and source field plate. Linear HVNW profile is obtained by linearity of HVNW mask. NLDMOS having blocking voltage of 100 V–300 V and lower On-resistance is developed based on 0.35um BCD Technology with less manufacturing cost. It is investigated that NLDMOS has poor performance over blocking voltage of 300V.

Different spatial charge trapping distribution effect on off-state degradation in power LDMOS was studied. Electron trapping phenomena is thermally grown in silicon dioxide (SiO 2 ). Due to charge can be trapped in the oxide, it can make structural defects, oxidation-induced defects, impurities, or other defects caused by Si-O-bond breaking process. This process can increase leakage current and cause off-state breakdown degradation. Many research already discussed about this mechanism, but not too much described about the distribution of charge trap into SiO 2 . In this paper, the distribution of charge trap in SiO 2 was studied in three different spatial charge distribution: Uniform, Gaussian, and Exponential using Sentaurus TCAD simulation software. This phenomena also studied at elevated temperature 150°C compare with room temperature.

The simulation tool is very important to develop process and design a new device structures. Device characteristics and physics phenomena also can be analyzed and predicted using this tool. But, it also have the limitation such us the physical model to describe the nature behaviours accurately. Selecting the models should be defined correctly. One of the critical processes is ion implantation because it is important to make a junction and determine the breakdown. For getting accurate results, the doping concentration profile in simulation should be calibrated with experiment, like Secondary Ion Mass Spectrometry (SIMS) profile. In this paper, Taurus analytical and Monte Carlo ion implantation model was investigated. The calibration will be difficult by using Taurus Analytical default Model. Using Taurus model by calibrating parameter can give a good agreement SIMS. Monte Carlo ion implantation model generally can give good profile prediction without calibration.