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Scanner mismatch has become one of the critical issues in high volume memory production. There are several components that contribute to the scanner CD mismatch. One of the major components is illumination pupil difference between scanners. Because of acceleration of dimensional shrinking in memory devices, the CD mismatch became more critical in electrical performance and process window. In this work, we demonstrated computational lithography model based scanner matching for sub 3x nm memory devices. We used ASML XT:1900Gi as a reference scanner and ASML NXT:1950i as the to-be-matched scanner. Wafer metrology data and scanner specific parameters are used to build a computational model, and determine the optimal settings by model simulation to minimize the CD difference between scanners. Nano Geometry Research (NGR) was used as a wafer CD metrology tool for both model calibration and matching result verification. The extracted pupil parameters from measured source map from both before and after matching are inspected and analyzed. Simulated and measured process window changes by applying the matching sub-recipe are also evaluated.