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With the continuous scaling in conventional CMOS technologies, the planar MOSFET device is limited by the severe short-channel-effect (SCE), Multi-gate FETs (MuG-FET) such as FinFETs and Nanowire, Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22 nm node. The multi-gate structure has better short channel behaviors due to enhanced control from the multiple gates. Due to the relatively more mature process and rich learning of the device physics, the FinFET is still extended to 5 nm technology node. In this paper, we proposed a 5 nm FINFET device, which is based on typical 5 nm logic design rules. To achieve the challenging device performance target, which is around 15% speed gain or 25% power reduction against the 7 nm device, we have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability. Based on our preferred device architecture, we provide our brief process flow, key dimensions, and simulated device DC/AC performance, like Vt, Idsat, SS, DIBL and parasitic parameters. As a part of the final evaluation, RO simulation result has been checked, which demonstrates that the Performance Per Area (PPA) is close to industry reference 5 nm performance.

In this work, an improved TCAD based Design Technology Co-Optimization (DTCO) is proposed for gate-all-around (GAA) Nanosheet FET (NSFET) at 3 nm technology node. Based on conventional DTCO, only an additional procedure is introduced to extract the SPICE model, while the huge computational expense in the TCAD simulation is saved. Compared to the 5 nm technology node, the performance of ring oscillator (RO) in the optimized 3 nm technology node increases by 30%, while the power decreases by 56%. Besides, dual-k spacer design for NSFETs at the device and circuit levels are also investigated.

In this paper, we proposed a 5 nm FINFET device, which is based on typical 5 nm logic design rules. We have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability. Based on our preferred device architecture, we provide our process key dimensions, and simulated device DC/AC performance, and some parasitic parameters. As a part of the final evaluation, Ring Oscillator (RO) simulation result has been checked, which demonstrates that the Performance Per Area (PPA) is close to industry reference 5 nm performance.

Since the logic 5 nm node still uses FinFET device, it still has room for device performance improvement since its first debut in the production of 16 nm node. The goal of this paper is to investigate the FinFET device optimization and Power Performance Area (PPA) at the 5 nm node. We have simulated FinFET device electrical characteristics at Front-End-Of-the-Line (FEOL) with Technology Computer Aided Design (TCAD). We first focus on the device with different spacer thicknesses to investigate DC and AC characteristics. Then we focus on the power and speed performance of Ring Oscillator (RO) circuits based on 5 nm NMOS and PMOS devices. Detailed study has been carried out to analyze the influence of Number of fins (Nfin), Back-End-Of-the-Line (BEOL) interconnect length, and fan-out number to power and speed. We hope that our results can assist other researchers in better understanding of the 5 nm FinFET device performance.

In the 5 nm FinFET design, more induced stress can bring charge mobility improvement and device performance. There are several influence factors on stress and mobility in the process design. Substrate orientation and channel direction combination is a early considered factor. The source/drain epitaxy (S/D epi) plays an important role in channel stress formation. The two steps in S/D epi, seed and bulk epitaxy processes play a different role in stress formation and mobility improvement. Fin structure is also an important factor in process design. We have found that a fin height of 50 nm for a 5 nm PMOS FinFET device can provide maximum hole mobility.

In 5 nm technology node, FinFET device performance is sensitive to the dimension of the device structure such as the fin profile. In this work, we simulate the influence of fin height and fin width to an n-type FinFET. We have found that an optimized fin height lies between 50~60 nm. The threshold voltage shift by quantum confinement effect has a steep increase as fin width shrinks to 4 nm. Sharper fin cross section profile gives better subthreshold swing (SS) and stronger drive current because of better gate control.

This paper introduces a device performance optimization approach for the FinFET through optimization of the gate length. As a result of reducing the gate length, the leakage current (I[Formula: see text]) increases, and consequently, the stress along the channel enhances which leads to an increase in the drive current (I[Formula: see text]) of the PMOS. In order to sustain I[Formula: see text], work function is adjusted to offset the effect of the increased stress. Changing the gate length of the transistor yields different drive currents when the leakage current is fixed by adjusting the work function. For a given device, an optimal gate length is found to provide the highest drive current. As an example, for a standard performance device with I[Formula: see text] = 1 nA/um, the best performance I[Formula: see text] = 856 uA/um is at L = 34 nm for 14 nm FinFET and I[Formula: see text] = 1130 uA/um at L = 21 nm for 7 nm FinFET. A 7 nm FinFET will exhibit performance boost of 32% comparing with 14 nm FinFET. However, applying the same method to a 5 nm FinFET, the performance boosting is out of expectance comparing to the 7 nm FinFET, which is due to the severe short-channel-effect and the exhausted channel stress in the FinFET.