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A phase shift technique using capacitive source degeneration (CSD) is presented for LC quadrature voltage-controlled oscillators (QVCO), where capacitively degenerated differential pairs are used to couple the LC tanks to implement a phase-shifted transconductance and negative input resistance to compensate resonator losses, and to minimize the flicker noise contributions. The CSD technique not only introduces excess phase shift to eliminate undesired bi-modal oscillation, but inherently provides a large coupling ratio to improve quadrature phase accuracy. Compared to existing phase-shift LC-QVCOs, the proposed CSD-QVCO presents excellent phase accuracy and power efficiency. A prototype of the QVCO was fabricated in TSMC 0.18-μm CMOS technology. The measured phase noise is -120 dBc/Hz at 3-MHz offset from 5-GHz carrier, with a power consumption of 6.4 mW from a 1.2-V supply.

A low power divide-by-8 injection-locked frequency divider is presented. The frequency divider consists of four current-mode logic (CML) D-latches connected in the form of a four-stage ring with the differential input signal injected into the clock terminals of the latches. The output signals can be taken from the data terminals of any of the four latches. The proposed frequency divider has higher operating frequency and lower power dissipation compared with conventional static frequency dividers. Compared with existing injection-locked frequency dividers, the proposed fully differential frequency divider presents wider locking range with the center frequency independent of injection amplitude. The frequency divider is implemented in TSMC 0.18 mum CMOS technology. It consumes around 3.6 mW power with 1.8 V supply. The operating frequency can be tuned from 4 GHz to 18 GHz. The ratio of the locking range over the center frequency is up to 50% depending on the operating frequency and biasing conditions.

For cellular handset ICs, integrating the power management unit (PMU) in the same chip as the baseband and the radio is critical for footprint and cost reduction, however, it presents unique challenges in terms of device reliability, bill of materials (BOM) and PMU performance. In this paper, a PMU integrated as part of a GSM/EDGE chip in a 65nm deep-Nwell CMOS process (Fig. 22.1.1), comprising a battery charger, a regulated inverting charge pump, multiple regulators. and a White LED (WLED) driver is presented. The battery charger supports various charging profiles up to V CHG =12V and can tolerate up to 20V. A regulated charge pump (CP) operating directly from the battery (V BAT ) provides negative supply for earphone class-AB audio power amplifiers (APA) for ground referred headset connectors. A buck converter and several linear regulators supply the various sub-systems on the chip as well as external modules (SIM Card/Camera/Interfaces etc.). An inductive-boost WLED driver drives up to 6 LEDs in series or up to 3 in parallel.

This paper presents two low-power demultiplexers working at 2.5 Gbps and 5 Gbps input data rate respectively. The 2.5 Gbps demultiplexer consumes only 6.8 mW power dissipation. The 5 Gbps demultiplexer consumes 42.5 mW power dissipation. The two demultiplexers are implemented in TSMC 0.35 /spl mu/m CMOS technology. They are built on the same chip sharing input and output ports. The power supply of the chip is 2.5 V. The demultiplexers are designed to be modules for optical communication receiver systems.