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Recent applications require vertical chip stacking to increase the performance of many devices without the need of advanced node components. Image sensors and vision systems will embed more and more smart functions, for instance, image processing, object recognition, and movement detection. In this perspective, the combination of Cu-to-Cu direct hybrid bonding technology with Through-Silicon-Via (TSV) will allow 3D interconnection between pixels and the associated computing and memory structures, each function fabricated on a separate wafer. Wafer-to-wafer hybrid bonding was achieved with multi-pitch design—1–4 µm—of single levels of Cu damascene patterned on 300 mm silicon substrates. Defect-free bonding, as far as the extreme edge of the wafer, was demonstrated on a stack with three wafers. Middle wafers thinning was done with grinding only and with a thickness uniformity (TTV)

Effects of additional thermal budget associated with a three-dimensional (3D) fabrication sequence are evaluated for the total-ionizing dose radiation response of fully depleted silicon-on-insulator (FD-SOI) MOSFETs. Current-voltage and low-frequency (1/ ${f}$ ) noise measurements are compared for (1) conventional planar FD-SOI MOSFETs, and (2) MOSFETs formed in the bottom layer of the 3D process and subjected to the process steps associated with formation of a second active layer. Similar radiation-induced voltage shifts and increases of 1/ ${f}$ noise are observed after irradiation for both types of structures. These similar changes in response show that the additional thermal processing involved with 3D fabrication has little effect on border-trap densities and radiation-induced charge trapping in gate and/or buried oxides of MOSFETs formed in the bottom layer of the 3D process.

Die-to-wafer direct hybrid bonding process is foreseen as a key enabler of heterogeneous 3D integration. Hybrid bonding technologies were first developed on W2W assembly reaching 3D interconnection pitch of $1\mu\mathrm{m}$ . Recently, CEA-Leti demonstrated the feasibility of DTW direct hybrid bonding at $10\mu\mathrm{m}$ with a specific die bonder (NEO HB) developed by SET Corporation. In this paper, the last improvements of DTW hybrid bonding process flow and die bonder alignment capability are presented. Main results showed an alignment capability improved to $ which enables bonding of die with $ interconnection pitch. Finally, multi-interconnection pitch bondings on a wafer were achieved with Cu pitches varying from $5\mu\mathrm{m}$ to $10\mu \mathrm{m}$ .

With the era of massive multi-core architecture targeting cloud computing for exascale high performance computing (HPC) and big data applications, large scale multi-core are made possible thanks to advanced 3D integration technologies. This paper presents an innovative concept of active silicon interposer with stacked chiplets, with the objective of maintaining overall power consumption budget, increasing chip to chip bandwidth, and preserving full system cost by smart system partitioning.

In the context of high-performance computing, the integration of more computing capabilities with generic cores or dedicated accelerators for artificial intelligence (AI) application is raising more and more challenges. Due to the increasing costs of advanced nodes and the difficulties of shrinking analog and circuit input output signals (IOs), alternative architecture solutions to single die are becoming mainstream. Chiplet-based systems using 3D technologies enable modular and scalable architecture and technology partitioning. Nevertheless, there are still limitations due to chiplet integration on passive interposers—silicon or organic. In this article we present the first CMOS active interposer, integrating: 1) power management without any external components; 2) distributed interconnects enabling any chiplet-to-chiplet communication; and3) system infrastructure, design-for-test, and circuit IOs. The IntAct circuit prototype integrates six chiplets in FDSOI 28-nm technology, which are 3D-stacked onto this active interposer in 65-nm process, offering a total of 96 computing cores. Full scalability of the computing system is achieved using an innovative scalable cache-coherent memory hierarchy, enabled by distributed network-on-chips, with 3-Tbit/s/mm2 high bandwidth 3D-plug interfaces using 20- $\mu \text{m}$ pitch micro-bumps, 0.6-ns/mm low latency asynchronous interconnects, while the six chiplets are locally power-supplied with 156-mW/mm2 at 82%-peak-efficiency dc–dc converters through the active interposer. Thermal dissipation is studied showing the feasibility of such approach.

Supercomputers will soon achieve Exascale-level computing performances mainly thanks to the introduction of innovative hardware technologies around the processors. This article explains architectural and performance evolutions and describes how 3D integration technologies have allowed heterogeneity and increased bandwidth that are decisive for hardware innovations contributing to Exascale.

In the context of high-performance computing and big-data applications, the quest for performance requires modular, scalable, energy-efficient, low-cost manycore systems. Partitioning the system into multiple chiplets 3D-stacked onto large-scale interposers - organic substrate [1], 2.5D passive interposer [2] or silicon bridge [3] -leads to large modular architectures and cost reductions in advanced technologies by the Known Good Die (KGD) strategy and yield management. However, these approaches lack flexible efficient long-distance communications, smooth integration of heterogeneous chiplets, and easy integration of less-scalable analog functions, such as power management [4] and system IOs. To tackle these issues, this paper presents an active interposer integrating: i) a Switched Capacitor Voltage Regulator (SCVR) for on-chip power management; ii) flexible system interconnect topologies between all chiplets for scalable cache coherency support; iii) energy-efficient 3D-plugs for dense inter-layer communication; iv) a memory-IO controller and PHY for socket communication. The chip (Fig. 2.3.7) integrates 96 cores in 6 chiplets in 28nm FDSOI CMOS, 30-stacked in a face-to-face configuration using 20µm-pitch micro-bumps (µ-bumps) onto a 200 mm2 active interposer with 40µm-pitch Through Silicon Via (TSV) middle in a 65nm technology node. Even though complex functions are integrated, active-interposer yield is high thanks to the mature 65nm node and a reduced complexity (0.08transistors/µm2), with 30% of interposer area devoted to a SCVR variability-tolerant capacitors scheme.

In the context of high performance computing (HPC), energy efficiency and computing density are key for targeting exascale architectures. Close integration of chiplets, active interposer and field programmable gate arrays (FPGA) paves the way for dense, efficient and modular compute nodes. In this paper, we detail the ExaNoDe multi-chip-module (MCM) combining the integration of a substrate, an active interposer, some chiplets and bare dice. The reported MCM demonstrates that the multi-level integration flow enables tight integration of hardware accelerators in a heterogeneous HPC compute node.

Die-to-wafer stacking is very promising for the next 3DIC generation since it offers the ability to assemble several dies with small interconnection pitches. This paper proposes an overall integration scheme D2W HB process to reinforce its robustness and its economical relevance for microelectronics industry. Firstly, a KGD strategy was developed to be compatible with hybrid bonding. A successful D2W bonding was demonstrated with tested pads. Secondly, the development of the planarization of stacked dies is presented.

With their attractive intrinsic properties, such as morphology, autoassembling properties, and tailorability, nano-objects could provide alternative and innovative routes to current microelectronics and nanoelectronics. Further insight on their electrical properties, especially in terms of statistics and reproducibility, as well as on their potential integration into silicon-based electronics is, however, often required to be able to fully exploit their potential. This paper proposes an innovative approach using a generic structure allowing the study of nano-objects electrical properties. Regarding the nano-objects integration, a homogeneous approach is presented with the in situ fabrication of atomic wires as a possible planar interconnection system. A heterogeneous approach is described as well with the characterization and preliminary integration of biological material, such as deoxyribonucleic acid-based nanowires or amyloid fibers.

The paper reviews the robustness/reliability achievements and include previously published data related to the hybrid bonding module for W2W and D2W bonding techniques.

We report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interconnects process and characterization. 3D packaging is presented up to the successful structural test and characterization of the demonstrator.

Die-To-Wafer hybrid bonding process is foreseen by major microelectronic industrials as essential for the success of future memory, HPC or photonic devices. However, compared to Wafer-To-Wafer bonding, the process flow is much more complex and the die assembly throughput is significantly reduced, which do not facilitate process industrialization. CEA-LETI is been working since several years on development of self-assembly process in order to overcome the throughput issue. The use of water drop is very promising to self-align several thousand of dies per hour. This paper presents the latest developments to improve self-assembly robustness and move a step forward toward manufacturing. Firstly, a new material benchmark enabled to identify a foundry compatible hydrophobic material. Secondly, we demonstrated that the die and substrate realization can be fully achieved on automatized equipments. Finally, the process setup on standard pick and place equipment significantly improved the self-assembly process robustness: 98% of the dies were perfectly bonded, and 63% presented an alignment lower than 1µm with a low 5µm die edge topography, which is compatible with hybrid bonding design.

Direct wafer bonding of wafers is now well establish. However in many interesting applications, direct bonding of die to wafer can lead to innovative devices. After explaining some specific fundamental mechanisms, III/V die to wafer bonding and copper hybrid bonding will be presented for photonic and 3D applications.

Cu/oxide Hybrid Bonding (HB) technology is currently the ultimate fine pitch 3D interconnect solution to reach submicron pitches. It's an attractive technique to address the needs of several applications such as smart imagers, high-performance computing and memory-on-logic folding. But test and characterization of such fine-grained 3D interconnect is still an open issue; Cu-Cu interconnects are prone to many structural defects due to fabrication process, such as misalignment, which needs to be thoroughly tested to ensure the performance of 3D-ICs. In this work, we focus on testing and characterizing, on-wafer, misalignment defect induced at the bonding step. A misalignment test structure was fabricated in a Wafer-to-Wafer (W2W) assembly configuration with a pitch of 3.42µm and 1.44µm using a very small measurement step for an accurate misalignment measurement (respectively 45nm and 22nm). Electrical tests have been performed using five multi-pitch wafers with 71 measurements points per wafer. The experimental results show that the results of the proposed test structure are aligned with conventional overlay measurements. Finally, the impact of misalignment defect on resistance and capacitance parameters was demonstrated.

This paper demonstrates an experimental micro- channel solution to cool microelectronic chips with hotspots, using an integrated, yet nonintrusive technique. In microelectronics, approaches such as die thinning induce acute stress on cooling because it increases the hotspot phenomena and reduces chip bulk thickness that could be used for microchannels. In compact devices, heat must be removed using limited pumping power and cooling space. Microchannels etched in the backside of the chip, usually considered as an efficient cooling solution, are impracticable on highly thinned chips. This paper experimentally investigates the cooling performance of a noninvasive and hotspot aware microchannel die that is in direct fluidic contact with the backside of the microelectronic chip. It also proposes a confinement-wise metric. A thermal resistance of 2.8 °C/W is achieved at a heat flux of 812 W/cm2 per heat source, for a total dissipated power of 20 W and a maximum allowed temperature rise of 55 °C. Such performance is obtained with only 19.2 kPa of pressure drop and 9.4 ml/min of flow rate, corresponding to a hydraulic power of only 3 mW and a coefficient of performance of 6500. In addition, the complete chip stack, including the thinned chip, measures only $660~\mu \text{m}$ high. Therefore, backside cooling appears to be a promising compact and low consumption solution for compact electronic applications having confined hotspots.

This article describes heat dissipation challenges in 3-D ICs; using two case studies, it also presents insights and design guidelines for 3-D thermal management.

Microelectronics industry aims at pushing the scaling of MOSFET devices, with a lot of challenges to solve for front-end and back-end processes. These challenges are also new opportunities, as for co-integration between silicon components and biological objects. In particular, bio-inspired nano objects such as DNA-based nanowires and protein-based nanowires have generated a huge interest based on their promising electrical properties [1, 2] and their size at the nanoscale. They could indeed bring a rich evolution in the nanotechnology community. This paper presents a common work performed by microelectronic biology and characterization teams which aims at describing the design, and the fabrication of a characterization platform dedicated to bio-inspired objects, and the first electrical measurements acquired on amyloid fibers. The design of this characterization platform takes into account biological and microelectronic constraints. Regarding biological constraints, special attention has been paid to materials choice and device fabrication in order to be biocompatible and to enable drop deposition for both wet and dry experiments. Dedicated patterns have been designed in order to measure electrical parameters such as contact resistance and resistivity of the bio-inspired objects. Regarding the fabrication step, the characterization platform has taken advantage from microelectronic technologies, especially in terms of size (nanoscale), reproducibility and robustness taken into account the specific environment. These aspects will be further discussed in this paper, as well as the first electrical measurements. To properly understand the electrical characteristics of bio-inspired objects, one critical point is the measurement of the linear conductivity of these objects, which implies the discrimination from contact resistance. Another important point is the conduction mechanism. Table 1 presents two patterns used to investigate the conduction mechanisms. To realize a complete electrical study, we have thus decided to design specific test structures as Transmission Line Matrix (TLM) and Van der Pauw patterns, structures with a variable electrode gap, and different contact areas structures. Figure 1 shows SEM images of the electrodes fabricated with this specific layout. The inter-electrode distance has been measured at 1µm and 70µm x 70µm square pads have been obtained. The figure 2 presents a cross section view of the fabricated electrodes. Electrode thickness is equal to 200nm and the width is equal to 1.7µm. Material impact and electrochemical properties of bio-inspired objects have also been investigated. Working with biological object at the nanoscale requires further restrictions. The main constraint is the use of biocompatible material to pattern all the layers in contact with the bio-inspired object. We have decided to use (i) platinum and gold because these metals are commonly used in biological measurements, and (ii) ruthenium due to its anisotropic etching properties. Another requirement relies on back gate electrode to enable the field effect investigation of bio-inspired object. To deal with wet measurement and to control the film deposition at the desirable position we have decided to engineer further cavities. Regarding packaging solutions, standard microelectronic metallic pads have been patterned to allow automated electrical characterization. Bioelectrical investigations as electrochemistry or control atmosphere measurements require the design of an “easy to plug” device enabling drop deposition and a very simple electrical connection adapted to electrical probers. This “easy to plug” device has been fabricated including a patterned silicon die assembled with a conductive glue on a Side-brazed Ceramic Dual In-inline Package (SCDIP) and wire-bonding. A SCDIP has been especially chosen to be easily carried and plugged inside biological equipment such as climatic chamber and glove box. Large package have been used in order to connect the maximum of patterns but also to provide an important protein-based nanowires density on the top of the electrodes. Figure 3 presents photography picture of the characterization platform used to perform the conduction measurements in biological equipment. The figure 4 presents the first electrical signal of the bio-inspired nano object which confirms that the characterization platform has been correctly fabricated and can be able to study the electrical properties of the protein film. This papers aims at presenting more details on (i) the design, (ii) the fabrication of silicon die in clean room (iii) the packaging adapted to the biological environment and (iv) results of electrical characterization of the bio-inspired objects at the nanoscale. References [1] D. V. Lim, M. M. Simpson, E. A. Kearns et al., Clin. Microbiol. Rev., vol. 18, no. 4, pp. 583–607, Oct. 2005. [2] F. S. Ligler and J. S. Erickson, Nature, vol. 440, no. 7081, pp. 159–160, Mar. 2006. Figure 1

Specific surfaces allowing Ultra-High Vacuum (UHV) investigations are required for the successful development of atomic nanostructures. Surface contamination, atomic roughness and defects density must be controlled in order to ensure the reliability of advanced UHV experiments. Surface preparation is a key parameter and is usually conducted in-situ in the UHV chamber. However the surface preparation requires a complex protocol. A microelectronic clean room environment enables the particles density control and enables 200mm wafer scale developments, especially Si(001)-(2x1):H surface reconstruction. However, this passivated surface is reactive and can be easily deteriorated, particularly during transportation. Consequently, a nanopackaging solution is proposed in order to provide a preserving environment for transportation. The nanopackaging process consists in the direct bonding of two passivated silicon surfaces, and is followed by a wafer dicing step into 1cm2 dies. Samples can be stored, shipped and in-situ opened without additional treatment. Furthermore, these samples can provide a reliable surface onto which molecular grafting can be accomplished. The fabrication modules and the associated characterization results will be described as well as atomic nanostructure manipulations and especially the grafting of a self-assembled monolayer using supercritical carbon dioxide as a medium.

3D vertical integration of components is today an industrial reality. To reduce pitch of interconnection between the dice, the hydrid bonding technique, offering sub-10 $\mu$m interconnection pitch, is widely demonstrated for Wafer-to-Wafer bonding. Die-to-Wafer direct bonding remains today more challenging due to additional particle contamination and handling complexity but presents interesting assets.The purpose of this paper is to demonstrate the performance of a fully automated Die-to-Wafer bonder, SET FC1, specifically designed for direct bonding dedicated to production. After a description of the process and the elements developed specially for this process, it will be demonstrated that an accuracy of ± 1 $\mu$m can be reached today with a throughput up to several hundred dice per hour. If progresses still need to be done, the particle contamination is low enough to enable demonstration of oxide/oxide Die-to-Wafer direct bonding. Considering the results obtained until now, industrialization appears feasible.

3D TSV integration enables scalable manycore architectures, however they require advanced cache coherence features to enable simple programming models. We propose TSARLET, a general purpose 16-core computing fabric targeting 3D TSV integration with a fully scalable cache coherent memory architecture, using distributed L2-caches, and adaptive fault tolerant L3-caches. Implemented in 28nm UTBB FDSOI technology, the circuit operates up to 1.15 GHz using adaptive clocking and provides 29 Gops/W in the 0.5-1.3V supply range. The chip's performance is demonstrated using an image filter application and an OpenMP based Convolutional Neural Network (CNN) on Linux.

Electronic systems require the integration of tightly coupled components manufactured with very dissimilar manufacturing technologies. Meeting the system requirements of performance, cost and power is a challenging task and new integration methodologies play a key role. A generalized cost model for 3D systems is presented that is applicable to both sequential and parallel 3D system integration. It takes into account yield multiplication effects in the case of sequential integration, and also reflects the additive nature of the cost for parallel integration. Example applications of this model are provided, starting with single chips undergoing Moore's law transitions, chiplets on interposers, wafer-to-wafer hybrid bonded components as well as chip-on-wafer 3D technologies.

International audience; Copper/oxide hybrid bonding process has been extensively studied these past years as a key enabler for 3D high density application with top and bottom tier interconnection pitch below 10μm. Since 2015 hybrid bonding process robustness has been confirmed on complete electrical test vehicles [1,2] as well as commercial products [3] integrating copper to copper interconnection pitchs close to 6μm. To our knowledge, no results have been shown today demonstrating sub-1.5μm pitch copper hybrid bonding feasibility.

One major step for 3D integration is the die stacking which has to meet mechanical and electrical requirements. Transient Liquid Phase bonding is studied because it is suitable with high interconnection density and also multiple stacking. For this study, top and bottom wafers including redistribution layers were electroplated with CuSn and Cu respectively. Die to wafer bonding was carried out at 250 °C in neutral atmosphere. Capillary underfill was added in some cases to check its influence. Interconnections quality was then assessed. Electrical tests were carried out using daisy chains. Shear tests enabled to check mechanical strength and failure location. Finally, cross sectional scanning electron microscopy and energy dispersive X-ray spectrometry allowed identifying metallurgical phases and potential defects. These characterizations were achieved before and after aging. This aging consisted either in thermal cycle test (TCT: 500 cycles between −40 °C and 125 °C with 10min soak time) or high temperature storage (HTS) applying the same thermal budget as during the TCT. After assembling, interconnections have very good electrical and mechanical properties. Their degradations are measured after TCT but they are larger than after HTS. This reveals failure mechanisms is not only based on chemical aging but also involve thermomechanical stress. This last feature has been limited thanks to underfill addition. Its effect was investigated through TCT where electrical yield drop was lower than when the gap between the die and the wafer is not filled. Moreover, SEM images reveal different kinds and densities of voids. Kirkendall voids are located at the Cu/Cu3Sn interface. Smaller voids are visible at the initial bonding interface in the case of CuSn to Cu bonding. After aging, some cracks develop mainly through Kirkendall voids which therefore seem to be the most detrimental defects to overcome.

3DIC integration is considered as one of the biggest revolutions coming in the next few years in microelectronics and assembly: revolution for the integration & process - from front end to 3D final assembly; revolution for supply chain, design tools, test and characterization...Impact of 3D process and stacking on Cmos and associated design rules that this integration will generate is a key point to ensure the real interest of 3D stacking. Many recent results tend to prove that some of those challenges are undertaken and on the good way to be solved: 2,5D integration, a step toward 3DIC, is already under production, and thus proposes some embryos of solutions. We can assume that when 2,5D will come with relevant yields and throughputs, the step toward 3DIC will be easier to climb. Nevertheless, 3DIC will come with specific challenges: thermal impact, coupling effect, stress impact...This paper is an overview of past and current work at Cea-Léti on those thematic. Among others, thermal modeling and characterization is given. Technological solutions at device level are proposed to reduce areas & impacts of hot points. Secondly, mechanical management of an interposer is detailed: especially with a large interposer, included high density of interconnections, warp management is a key point during 3D process steps, but also during 3D assembly. For this thematic also, some characterizations are given with some proposed solutions. Finally, a review of major 3D technological steps with associated possible impacts on performances is given. It gives both the already done work, and some of the challenges still to address.

Graphite-based materials have been proved to be an enhancement over copper heat spreaders when directly integrated at the silicon level. However, not only they outdo copper in terms of thermal performance, but their in-plane CTE (coefficient of thermal expansion) is much closer to that of silicon. As a result, mechanical stress due to deformation mismatches is reduced during thermal cycling. Thus, thermal interface thickness can be reduced to optimize the heat flow from the hotspot. Heat management of 3D structures implies several challenges. The silicon die and intertier thickness are limited by the vertical connexions height in these heterogeneous stacks. These constraints will also imply strongly thinned heat spreaders and thermal interfaces in a future intertier implementation. This work investigates the thermo-mechanical constraints of integrating a heat spreader at the die level. Copper and PGS (pyrolytic graphite sheet) heat spreaders are compared. Their deformation subjected to thermal cycling is measured experimentally via Thermo-Moire measurements. The differences in the deformation between the silicon die, molding and the substrate are also measured.

This paper proposes an extensive analysis of the impact of both structural effect and charge parameters on silicon nanowire-based biological sensors, for single-charge detection. These parameters are calibrated on physical and electrical characterizations and are subsequently introduced in a compact model to predict the signal over noise ratio (SNR). We finally propose rules for the design of nanowires and recommendations for the placement of the biological element, inducing the single charge release.

Direct hybrid bonding is considered as one of the most promising technologies for high performance 3D-ICs. Its face-to-face structure allows significant inter-connexion capabilities. Nonetheless, it also implies increased thermal densities that will be reflected in both die tiers due to the lack of insulating barriers. This work investigates the thermal interactions between two hybrid bonded dice for different case scenarios. A specific test vehicle comprising heaters and temperature sensors have been designed. Packaging variables such as silicon thickness, substrate thermal design or TIM conductivity and thickness are studied.

By shortening communication distance across dies, 3D technologies are a key to continued improvements in computing density. For 4G telecom baseband processing, specific computing units arranged in a regular network-on-chip (NoC) array provide power-efficient computation [1]. However, for advanced MIMO processing, more computing power is required when the number of antennas increases. This paper presents a homogeneous 3D circuit composed of regular tiles assembled using a 4×4×2 network-on-chip, using robust and fault tolerant asynchronous 3D links, providing 326MFlit/s @ 0.66pJ/b, fabricated in CMOS 65nm technology using 1980 TSVs in a Face2Back configuration.

3D integration so far has often been investigated through a face to face point of view: the top die FEOL is in front of bottom die FEOL. This allows a dense connectivity between both dies, but TSV are mandatory on the bottom die for each external exchange. Another flow chart, which main application is identified as the Wide I/O, is “face to back”: the FEOL of the top die faces to the back side of the bottom dies. To communicate between top & bottom, interconnections then TSVs are needed. Advantage is that the bottom die, for Wide I/O the logic dies, faces directly to the board allowing a rapid communication with external. Also, the Wide I/O interface delivers high bandwidth at relatively low power consumption level. The objective of this paper is to show latest integration at Leti, both on 200mm & 300mm wafers, using face to back integration. If we compare both flow charts, using via middle technology, the main challenge consists of the temporary bonding. The temporary adhesive needs to be at least 50 μm thick, even more depending on staking technology on board, and in presence of the macro connection. The choice of the adhesive is crucial for the final stability of the stack during back side process and also during debonding, even more on 300mm wafers. Technical developments are introduced in the paper. A specific focus is done on temporary adhesive & the associated thermal stability of the stack. Impact of the temporary bonding on copper pillar is evaluated. Assembly of best processes for a full integration on daisy chain wafers, both 200 & 300 wafers is described. Finally, a comparison of electrical datas (resistance, capacitance, isolation) for both wafer diameters is given. Morphological characterization finalizes this first integration and leads to further potential improvements.

From low density 3D integrations embedding Via Last Through Silicon Vias (TSV) to high densities hybrid bonding or 3D VSLI CoolCubeTM solutions, a multitude of new product opportunities is now envisioned. An overview of existing emerging 3D integrations is provided covering Image sensors, Photonics, MEMS, Wide I/O memories and Silicon Interposers for advanced logics. Associated key challenges and developments are highlighted focusing on 3D platform performance assessment.

International audience; 3D integration technology is nowadays mature enough, offering today further system integration using heterogeneous technologies, with already many different industrial successes (Imagers, 2.5D Interposers, 3D Memory Cube, etc.). CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, µ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes. In this paper, a short overview of some recent advanced 3D technology results is presented, including some latest 3D circuit's description.

We present our recent developments on silicon technologies dedicated to the packaging of nano-objects/nano-devices. These technologies aim at both protecting and electrically connecting a nanoscale device positioned on a perfect Si(001)-(2 × 1):H surface smoothed thanks to a 950 °C thermal treatment. The nano-device is connected to nanopads implanted on the silicon surface. Each nanopad is linked to a nanovia which is locally achieved by etching and filling processes operated in a FIB (Focused Ion Beam) equipment. Impacts of the FIB process on via morphology and properties are depicted. Nanopads are fabricated through the local implantation of arsenic, and the effect of the surface smoothing thermal treatment on the dopants diffusion length is estimated by simulation and then experimentally explored. Key process steps such as the etching of a deep cavity and the surface protection with a temporary cap are also described, and a first assembly consisting in a substrate equipped with nanopads and directly bonded with a cap substrate is presented.

We present an advanced and comprehensive platform for thermal dissipation studies in TSV-based 3D ICs. A 2-tier 3D test chip with through silicon via (TSV) and μ-bump is used for thermal characterization with unprecedented precision and design exploration capabilities. A comprehensive calibrated 3D finite element model is associated to provide a predictive tool that is able to simulate the thermal mapping in any given 3D interconnect configuration with minimal error. Guidelines are finally provided for thermal optimization of 3D designs with a precision far beyond the prior art.

Heat generation in integrated circuits has become in few decades one of the most limiting factors for performance improvement in mobile device components, such as cell phones or tablets. In these devices, heat dissipation is limited to a few Watts as state of art cooling systems, such as heat-sinks or fans, do not fit with the dimensional and power consumption constraints. Amongst the solutions proposed for circuit cooling, the implementation of heat spreaders is probably the most suitable alternative for compact packages due to their ease of manufacturing and low cost. The objective of this work is therefore to study the performance of a high thermal conductivity layer directly integrated at the die level in the scope of short term industrial implementation. In particular, we compare both the hotspot temperature reduction and the temperature profile of the die using either copper or a graphite based material. Temperature reductions over 80°C have been measured for the best case scenario, with a thermal resistance enhancement of 61% at the die stack level. Finite volume simulations are finally presented in order to explain the thermal flux of the system.

This paper is dedicated to the full integration of a new silicone-based material for Molding-Underfilling (MUF) on silicon interposer wafers containing Through Silicon Vias (TSVs) and top dice. The developments were carried out in the frame of “silicon package” where the silicon interposer is either reported on P-BGA or directly assembled on board. After a materials screening with regard to warpage issue, “molding last” was studied with the selected material, including compatibility with temporary bonding debonding, bumping, sawing and report on organic substrate. A focus is made on void-less molding-underfilling process development and wafer level reliability evaluation of first level (die to wafer) interconnections and TSV subjected to thermal cycles. For this study, a molding-last approach using a dry-film lamination process has been chosen. 170μm thick dice have been assembled on 120μm thin silicon interposers having 60μm diameter TSV via-last and encapsulated with optimized wafer-level MUF process. Electrical performances of the 35μm high Cu pillars interconnections have been measured on the interposer backside thanks to TSVs and rerouting. While the daisy chains resistances remained in specifications after molding and pre-conditioning, some electrical failures appeared after 250 thermal cycles. Cross-sections have highlighted cracks in solder joints leading to the development of an improved version of the compound. Finally, a complete test vehicle with a molded-underfilled interposer reported on an organic substrate has been achieved.

This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.

The purpose of this paper is to investigate integration results of 300mm silicon wafers thinned at 80μm down to 50μm using the innovative temporary ZoneBOND™ technology to handle the device during the process flow. A focus on the coating/bonding and thinning process of 80μm and 50μm thick silicon interposers is made. A tape selection study enabled us to identify two separation tapes compatible with varying interposer backside topology as well as the adhesive cleaning chemistries. After the validation of these fundamental processes, we created fully-functional interposers presenting 10×80 μm or 6Χ55μm TSVs. We measured the TTV and deformation through all the thinning and the backside processes. No significant TTV difference has been observed and all steps whatever the interposer type successfully pass the integration process. Finally, in order to increase the process window of the dielectric and TSV CMP, different oxide deposits are tested on 300mm temporary bondings thinned at 80μm or 50μm. This study confirmed that the dielectric deposition process remains one of the most challenging steps of the backside process. It has been observed that the use of hard mask type deposition process does not damage temporary bonding interface whereas TEOS type deposits at 200°C initiate damage at bonding edges which are more significant for 50μm interposer and thicker deposition layers. This work concludes on the process limitations with the use of ZoneBOND™ technology.

This study focuses on the prototype of a 3D circuit in 65nm CMOS node, in which digital and analog functions have been partitioned on two different layers, assembled in a face-to-face integration and reported on a BGA. The paper more specifically presents the process technology carried out for the realization of the bottom die. Major process steps are described and evaluated from an electrical performance point of view.

This paper deals with the performances of Wafer-Level UnderFill in ultra-fine 50 microns pitch interconnections. Firstly, dry-film WLUF assembly feasibility has been demonstrated by checking lamination and planarity in the pillar areas. Well-formed Pb-free joints have been obtained after thermocompression with limited void or WLUF entrapment. Secondly, to have a better understanding of this innovative material performances during thermal and moisture tests, the electrical behavior of Copper pillars chains surrounded by WLUF has been compared with those surrounded by classic Capillary Underfill used in the semiconductor industry. We have successfully demonstrated that chains surrounded by WLUF are stable during JEDEC level 4 preconditioning and moisture storage. During thermal cycling, behavior variation of chains surrounded by WLUF has been observed, depending on interconnects quantity. However, electrical performances of the longest 100 pillars chain respond to industrial specifications and are similar for both underfill. After thermal and moisture tests, a good adhesion of WLUF stacks has been verified by shear tests. Those results have demonstrated the pertinence of this innovative WLUF material with 50µm pitch interconnections.

In this paper, high density TSV integration in silicon interposer is presented, fully characterized and simulated (DC and RF). Parasitic elements of the RF model are extracted. Dielectric and metal process improvements are developed and their impact on TSV RF behaviour is evaluated. At least, silicon resistivity effect on TSV RF performances is demonstrated.

Today, a new trend in wafer level packaging is to add more than one die in the same package and, sometimes, to use the third dimension in order to : • Decrease the form factor of the final system • Improve the thermal and electrical performances of the device • Decrease the cost of the final product In order to stack the heterogeneous components in the third dimension, TSV (Through Silicon Vias) is a very promising technology compare to wire bonding. In this paper, the technological bricks specifically developed for 3D integration demonstrator will be presented. The integration flow was based on the 45 nm technology top chip stacked on a 130 nm technology active bottom wafer [1] [2]. This flow needed to develop specific wafer level packaging technologies such as: • Top chip & bottom chip interconnections • High aspect ratio TSV included into the bottom wafer • Backside interconnections for subsequent packaging step • Temporary bonding and debonding of bottom wafer [3] [4] • Top chip stacking on bottom wafer In the first part of the paper, the complete process flow will be presented. Then, a technical focus will be done on the specific steps developed for the improvement of the TSV's electrical performances. Finally, the electrical results achieved on a specific test vehicle, similar to the demonstrator will be discussed. The electrical results obtained on a technological test vehicle will be firtly presented. Those results include electrical continuity, pillars resistance, TSV resistance and capacitance and TSV insulation and current losses. Then, the electrical results obtained with the “high electrical performances” process on the functionnal demonstrator will be showed, including a specific focus on the TSV capacitance measurements.

We present in this paper the two generic integration schemes developed at Leti, aiming to address two opposite industrial needs. The first scheme, based on TSV free Via Belt technology, allows wafer level integration of highly heterogeneous systems taking into account different technologies, wafer and die sizes and mainly targets enduser companies looking for generic technologies. The second one, based on TSV WLP and active silicon interposer, mainly addresses the IDMs needs. Main technological bricks related to both schemes are presented and validated through specific demonstrators.

System integration takes benefit from 3D stacking technologies in a wide range of applications such as imagers, stacked memories, mobile applications and high-performance computing. Several integration schemes are considered worldwide to address applications specific requirements: performance, cost, form-factor, thermal management or even supply chain availability. Nevertheless, most of the available technologies cannot offer ultra-fine pitch interconnect, below $10 \mu \mathrm {m}$. This paper presents two 3D-high density (with 3D interconnects pitch around or below the $\mu \mathrm {m}$ range) schemes using on one side direct hybrid bonding and on the other one monolithic integration. Both integrations are described and current status are given. A technology/application roadmap is proposed positioning both integrations and showing that they offer complementary approaches to tackle most of today challenges in terms of cost, area, power and performance.

In the wide range of emergent nanotechnologies, DNA-based microelectronics has shown an important potential for components miniaturization and auto-assembling approaches applicable to future silicon-based electronic circuits [1]. In order to pursue the Moore's law, interconnections must be indeed addressed at the nanoscale, with a good control of their size, location and electrical & thermal performances. With its natural auto-assembling property, its 2-nm-double-helix diameter and its several metallization possibilities, DNA is a promising candidate to build bio-inspired electronic components [1]. DNA has been first metallized by Erez Braun in 1998 using a silver electroless method [2]. Since 1998, several groups have worked on DNA metallization using different chemistries with metals such as Pd, Pt, Au, Ag and Cu [3]. Most of these works have presented electrical and morphological characterizations of few metallic nanowires. However, in order to initiate DNA-based-nanowires integration on silicon technologies, we must start to implement nanowires on silicon at wafer scale. We have thus developed a platform based on silicon technologies providing morphological and electrical characterizations of copper nanowires built from DNA [4]. This platform will allow us to simultaneously characterize a large number of nanowires, returning a statistic of their electrical performance, and thus allowing the optimization of the copper nanowire metallization process. Two main approaches are proposed to fabricate and contact a large number of copper nanowires with metallic electrodes in order to study their electrical behavior. In both approaches, a linear 16-μm-length DNA phage is used. The first approach consists in aligning DNA wires on a hydrophobic silicon oxide surface by a method called DNA combing. On a second time, aligned DNA wires are all metallized by electroless process [4]. 5-nm-diameter copper nanowires have been so far achieved by this method and focus on improving the metallization process is currently at stake. Finally, Ti/Au electrodes are fabricated on the nanowires by a classical lift-off process in order to electrically connect them. The advantage of this approach is the very accurate nanowires alignment and their homogeneity over the surface. However, the low number of aligned nanowires per surface unit (10–20μm−2) and the high electrical resistance of each (>kohms) makes the electrical characterization quite complex. On the other side, the second approach consists in fabricating the Ti/Au electrodes first and then aligning or randomly depositing the copper nanowires at their surface. Same protocols are used to align and metallize the DNA nanowires for both approaches. The advantage of this second approach is a higher nanowire density deposited on the electrodes. However, a higher contact resistance and a lower control of nanowires alignment are obtained. Both approaches are currently explored and permit to explore a wide range of parameters for copper nanowires metallization process improvement.