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Artificial intelligence (AI) is increasingly used to solve multi‐objective problems and reduce the turnaround times of semiconductor processes. However, only brief AI explanations are available for process/device/circuit engineers to provide holistic feedback on the manufactured results. Herein, linear/nonlinear variation decomposition (LVD/NLVD) of neural networks is demonstrated to quantitatively evaluate the influence of unit processes on the figure of merit (FoM) and co‐analyze the unit process influences with device characteristic behaviors. The NLVD can evaluate the output variation from each input of neural networks in an individual sample, although neural networks are not available in an analytic form. The NLVD is successfully verified by confirming that a) the output and summation of all decomposed output variations perfectly coincide and b) the process influences on the FoM are decomposed to 6.01–54.86% more accurately compared with those of LVD in 1Y nm node dynamic random‐access memory test vehicles with a baseline and split tests introducing high‐k metal gates with a minimum gate length of 1 A nm node for further node scaling. The approaches identify defective processes and defect mechanisms in each sample and wafer, which enhance causal analyses for individual cases in diverse fields based on regression artificial neural networks.

Neural compact models are proposed to simplify device‐modeling processes without requiring domain expertise. However, the existing models have certain limitations. Specifically, some models are not parameterized, while others compromise accuracy and speed, which limits their usefulness in multi‐device applications and reduces the quality of circuit simulations. To address these drawbacks, a neural compact modeling framework with a flexible selection of technology‐based model parameters using a two‐stage neural network (NN) architecture is proposed. The proposed neural compact model comprises two NN components: one utilizes model parameters to program the other, which can then describe the current–voltage (I–V) characteristics of the device. Unlike previous neural compact models, this two‐stage network structure enables high accuracy and fast simulation program with integrated circuit emphasis (SPICE) simulation without any trade‐off. The I–V characteristics of 1000 amorphous indium–gallium–zinc‐oxide thin‐film transistor devices with different properties obtained through fully calibrated technology computer‐aided design simulations are utilized to train and test the model and a highly precise neural compact model with an average IDS error of 0.27% and R2 DC characteristic values above 0.995 is acquired. Moreover, the proposed framework outperforms the previous neural compact modeling methods in terms of SPICE simulation speed, training speed, and accuracy.

Herein, the impact of cross‐temperature on 3D NAND flash memory is modeled by considering adjacent cells using machine learning. The cells comprising NAND flash memory exhibit diverse states and connectivity patterns. To effectively capture this complexity, the 3D NAND flash is converted to graph structure and the graph neural network (GNN) is leveraged, known for its exceptional performance in handling graph data. To the best of the authors' knowledge, this is the first attempt to model 3D NAND flash memory using GNN. This method has good generalization performance across various retention times and temperatures, achieving a remarkable overlap of 95.28% between ground truth and predicted distributions. Moreover, two applications of this method are introduced that contribute to the NAND flash memory improvement. One is a GNN‐assist program, which leverages well‐trained GNN to suppress the Vth degradation affected by cross‐temperature, resulting in reduced Vth shift and narrower Vth distribution width. The other is the sensitivity decomposition to identify parameters influencing the cell at cross‐temperature. It is found that cross‐temperature impact extends beyond physically connected cells to adjacent cells at close distances. Overall, this work provides valuable insights into modeling 3D NAND flash memory using GNNs and offers practical methods for enhancing NAND flash memory reliability.

Herein, novel neural network (NN) methods that improve prediction accuracy and reduce output variance of the optimized input in the gradient method for cross‐sectional data are proposed, and the variability evaluation approach of optimized inputs in the semiconductor process is suggested. Specifically, electrical parameter measurements (EPMs) and power‐delay product of industrial high‐k metal gate DRAM peripheral 29‐stage ring oscillator circuits, including NMOS, PMOS, and interconnects, are focused on. The proposed methods find an optimized input to achieve a lower NN output variance in the gradient descent than one multilayer perceptron (MLP) and mean ensemble of MLPs even when considering the variabilities of the devices and interconnects. The local optima problem of one MLP is resolved by utilizing multiple MLPs trained with different train/validation data, their trimmed mean, and an additional learnable layer. Moreover, adding the learnable layer secures versatility for various parametric datasets. The methods improve the prediction accuracy (R2) by 5.6–15.6% in sparse data space compared to one MLP and the mean ensemble, decrease the NN output variance of the optimized input by 73.0–81.6% compared to one MLP and the mean ensemble, and are successfully verified by implementing it on EPMs of 3977 test patterns of 314 wafers and 16 lots.