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Essential design requirements for a sense amplifier (SA) used in the resistance monitoring write termination (RM-WT) scheme are suggested to reduce the write energy of spin-transfer-torque random access memory (STT-RAM) while achieving a write pass yield comparable to that of a conventional write operation. In addition, a self-referenced single-ended RM-WT (SS-RM-WT) scheme is proposed. To reduce the offset voltage, a single-ended sensing circuit (SE-SC) is used in the SA. A data-aware input voltage-transfer method is also adopted in the SE-SC to maximize the input voltage difference. By adopting a capacitor between the output of the SE-SC and the input of an inverter generating a logical output used for the write termination, the conflict between maintaining and changing the output of the SE-SC is resolved. The simulation results using the industry-compatible 65-nm technology HSPICE model parameters show that the proposed SS-RM-WT scheme achieves a 44% write energy saving on average without increasing the write error rate. Area overhead is only 11.8% for a 256-kb STT-RAM array, whereas that of the previous self-referenced RM-WT schemes is up to 42.5%.

This brief presents a review of developments in spin-transfer-torque magnetoresistive random access memory (STT-MRAM) sensing over the past 20 years from a circuit design perspective. Various sensing schemes are categorized and described according to the data-cell variation-tolerant characteristics, pre-amplifiers, and offset tolerance. Key breakthroughs for achieving the optimal reference scheme, read disturbance prevention, read energy reduction, accurate yield estimation, and overcoming other non-idealities are discussed. This review is intended to facilitate further enhancement of STT-MRAM sensing in advanced technology nodes, thereby fulfilling STT-MRAM’s potential as a universal memory.

Recently, with the increase in popularity of Internet of Things (IoT) devices, cryptographic protection techniques have become necessary for high-security applications. In general, IoT devices have strict power and area constraints. Thus, use of a physical unclonable function (PUF), which can generate a secret key at low cost, can be advantageous for high-security IoT devices. This paper presents a novel environmental-variation-tolerant (EVT) magnetic tunnel junction (MTJ)-based PUF that has a small area, high randomness, and low bit error rate (BER) compared to previous PUFs. The simulation results obtained using industry-compatible 65-nm model parameters indicate that the proposed PUF exhibits an inter-chip Hamming distance of 0.4901 and entropy of 0.9997, which proves the randomness of the PUF response. In addition, the proposed PUF exhibits the lowest BER across a wide voltage range (0.9 V–1.3 V) and temperature range (−25 °C – 75 °C) compared with previous PUFs.

In recent years, Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has been considered as one of the most promising non-volatile memory candidates for in-memory computing. However, system-level performance gains using STT-MRAM for in-memory computing at deeply scaled nodes have not been assessed with respect to more mature memory technologies. In this letter, we present perpendicular magnetic tunnel junction (pMTJ) STT-MRAM devices at 28nm and 7nm. We evaluate the system-level performance of convolutional neural network (CNN) inference with STT-MRAM arrays in comparison to Static Random Access Memory (SRAM). We benchmark STT-MRAM and SRAM in terms of area, leakage power, energy, and latency from 65nm to 7nm technology nodes. Our results show that STT-MRAM keeps providing $\sim 5\times $ smaller synaptic core area, $\sim 20\times $ less leakage power, and $\sim 7\times $ less energy than SRAM when both devices are scaled from 65nm to 7nm. With the emerging need for low power computation for a broad range of applications such as internet-of-things (IoT) and neural network (NN), STT-MRAM can offer energy-efficient and high-density in-memory computing.

In the design of nonvolatile memory (NVM), the sensing scheme (SS) has become a read-energy bottleneck because the required read-cell current is too large to satisfy a target read yield. This problem is further aggravated by technology scaling because increased process variation and reduced supply voltage ( $V_{\mathrm {DD}}$ ) require more current to satisfy the target read yield. This paper proposes an offset-canceling single-ended SS (OCSE-SS) with one-bit-line precharge architecture (1BLPA) that is intended for use in ultralow power NVM applications. The test chip is fabricated using 65-nm process technology, and the measurement results show that the read energy per bit of the OCSE-SS is 1/3 compared to that of the conventional SS (Conv-SS). The read energy reduction comes from the single-ended sensing, offset cancellation, and 1BLPA features. Moreover, when a resistance difference between the data and reference cells is as small as $0.5~k\Omega $ , the OCSE-SS reads successfully with a $V_{\mathrm {DD}}$ of 1.0 V and a sensing time ( $t_{\mathrm {SEN}}$ ) of 17 ns due to the offset cancellation characteristic, whereas the Conv-SS fails regardless of $V_{\mathrm {DD}}$ and $t_{\mathrm {SEN}}$ values.

For ultra-low-power Internet of Things (IoT) devices powered by batteries or energy harvesting, a nonvolatile flip-flop (NV-FF) operating in the near-threshold voltage (NTV) region has been widely studied to save both standby and active power. However, in the NTV region, the NV-FF suffers from restore yield and performance degradation due to the increase in process variation combined with the decrease in supply voltage. This paper presents a comparative analysis of the previous NV-FFs according to supply voltage scaling and suggests the design directions for implementing the NV-FF that can operate with compact area and high performance even in the NTV region. Through the comparative analysis, a novel offset-cancellation sensing-circuit (OCSC)-based NV-FF, which adopts a separate latch and sensing circuit structure and an offset-cancellation technique, is proposed. The Monte Carlo HSPICE simulation results using industry-compatible 65-nm model parameters show that the proposed NV-FF satisfies a target restore yield with 32% area, 88% speed, and 82% energy savings in comparison with a representative NV-FF of the merged latch and sensing circuit structure.

This paper demonstrates that the read output voltage difference between data and reference voltages in a resistive non-volatile memory is not a Gaussian distribution but composed of two Gaussian distributions. In addition, a tail fitting method is proposed to estimate a read yield with high accuracy. Monte Carlo HSPICE simulation results based on industry-compatible 45-nm model parameters show that the proposed tail fitting method improves accuracy by $\mathbf{5.2\ x}$ and $\mathbf{2.5\ x}$ compared to the normal fitting and the importance sampling methods, respectively.

The STT-MRAM technology is a promising candidate for future on-chip cache memory because of its high density, low standby power, and nonvolatility. As the technology node scales, especially under 40-nm technology node, STT-MRAM cell design becomes a key issue to approach low power consumption, high access performance, and desirable reliability. The conventional 1T-1 magnetic tunnel junction (MTJ) and 2T-2MTJ cell designs cannot address these challenges efficiently. In this paper, we propose a novel 3T-3MTJ cell structure using the advanced perpendicular MTJ (p-MTJ) technology. It can store 2 bits with three MTJs. The differential sensing technique can be used to read out the most significant bit as fast as the 2T-2MTJ design. The sensing latency of 2 bits within the same cell is almost the same as the sensing latency of the 1T-1MTJ cell design. Therefore, the 3T-3MTJ cell can have the advantages of both 2T-2MTJ and 1T-1MTJ cells. Circuit-level simulations show that the proposed 3T-3MTJ cell structure can achieve a desirable tradeoff between storage density, access performance, and energy consumption compared to the prior 1T-1MTJ and 2T-2MTJ cell structures. Additionally, we propose a novel adaptive cache design based on the 3T-3MTJ cell structure, which can work in different modes to satisfy various memory access demands from different applications. Architecture level simulations validate the effectiveness of the proposed cache design.

In the spin-transfer-torque random access memory design, the sensing scheme has become a bottleneck from the viewpoints of performance and read energy, because the required read current and time are too large to satisfy a target read yield. When the target read yield is greater than the fundamental read-yield limit determined by bit-to-bit data-cell variation, the conventional data-cell-variation-tolerant (DCVT) sensing scheme cannot satisfy the target read yield without requiring impractically high performance and energy overhead. To resolve this problem, this paper proposes a DCVT dual-mode sensing scheme (DMSS) that operates mostly in normal mode when correct sensing is assured, and infrequently in exception mode when correct sensing is uncertain. Using the dual-mode strategy, the DMSS can achieve the target read yield, while significantly mitigating the performance and energy overhead. Monte–Carlo HSPICE simulation results, using industry-compatible 45-nm model parameters, show that the proposed DMSS achieves a read yield of 6.1 sigma with a $3.2\times$ faster read time and $4.5\times$ lower read energy than the destructive self-reference sensing scheme.

Magnetic tunnel junctions integrated for spin-transfer torque magnetoresistive random-access memory are by far the only known solid-state memory element that can realize a combination of fast read/write speed and high endurance. This paper presents a comprehensive validation of high endurance of deeply scaled perpendicular magnetic tunnel junctions (pMTJs) in light of various potential spin-transfer torque magnetoresistive random-access memory (STT-MRAM) use cases. A statistical study is conducted on the time-dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, pulsewidth, duty cycle, and temperature. The experimental results coupled with TDDB models project $> 10^{15}$ write cycles. Furthermore, this work reports system-level workload characterizations to understand the practical endurance requirements for realistic memory applications. The results suggest that the cycling endurance of STT-MRAM is “practically unlimited,” which exceeds the requirements of various memory use cases, including high-performance applications such as CPU level-2 and level-3 caches.

Resistive nonvolatile memory (NVM) is considered to be a leading candidate for next-generation memory. However, maintaining a target sensing margin is a challenge with technology scaling because of the increased process variation and decreased read cell current. This paper proposes an offset-canceling current-sampling sense amplifier (OCCS-SA) that is intended for use in deep submicrometer resistive NVM. The proposed OCCS-SA has the three major advantages of: 1) offset voltage cancellation; 2) double sensing margin structure; and 3) strong positive feedback. The measurement results from a 65 nm test chip show that the proposed OCCS-SA achieves 2.4 times faster sensing time ( $t_{\mathrm {\mathbf {SEN}}}$ ) at a nominal supply voltage ( $V_{\mathrm {\mathbf {DD}}}$ ) of 1.0 V and a greater than 20% reduction in $V_{\mathrm {\mathbf {DD}}}$ at the same $t_{\mathrm {\mathbf {SEN}}}$ , compared to the state-of-the-art current-sampling-based SA, which features offset voltage cancellation and weak positive feedback.

This paper investigates the temperature-dependent behaviors of critical device parameters in 1 Gb perpendicular magnetic tunnel junction (pMTJ) arrays from 25 °C to 125 °C. Despite the fact that pMTJ (45-50 nm in diameter) attributes are generally degraded at elevated temperatures, this paper suggests that an adequate combination of critical device parameters can be obtained through systematic materials and process engineering, including H c (1760 Oe at 25 °C versus 750 Oe at 125 °C), H OFF (

Spin-transfer-torque random access memory (STT-RAM) has attracted much research interest because of its characteristics of nonvolatility (i.e., zero standby power) and small cell size (i.e., high density and high performance). As the technology node is scaled down, however, the sensing margin of the STT-RAM is degraded because of the increased process variation and reduced supply voltage. To improve the sensing margin, this brief focuses on a reference scheme design capable of reducing the reference resistance distribution. A multiple-cell reference (MCR) scheme is proposed that achieves the narrow reference resistance distribution. Moreover, the MCR scheme does not exhibit parasitic mismatch, regularity problem, read disturbance, and write current degradation, and it also has small area overhead.

As the technology node scales down, the spin-transfer-torque random access memory (STT-RAM) has been considered as a promising memory solution owing to its scalability. However, the increased process variation and the reduced supply voltage lead to degradation in the sensing yield (SY) as well as an increase in the read disturbance probability. Temperature variation further aggravates this phenomenon. Thus, achieving a target SY with a lower sensing current in all process, voltage, and temperature (PVT) corners has become an important issue in a deep-submicrometer technology node. In this paper, we propose a corner-aware dynamic gate voltage scheme to achieve constant-current sensing, regardless of the PVT variations. By adopting this scheme, the state-of-the-art sensing circuits (SCs) can significantly reduce the sensing current, while achieving the target read yield. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the offset-canceling dual-stage SC that uses the proposed scheme satisfies a target SY of six-sigma (96.34% for 32 Mb) with two times lower sensing current and two times lower read energy compared with that using a fixed gate voltage.

Spin-transfer-torque random access memory (STT-RAM) has attracted much research interest for its characteristics of scalability, nonvolatility, and small cell size. As the technology node is scaled down, however, the sensing margin (SM) and read disturbance margin (RDM) of the STT-RAM are degraded because of increased process variation, decreased supply voltage, and reduced critical switching current. In this brief, we propose a half-pulsewidth read disturbance (HPWRD) scheme that is capable of significantly improving the RDM by reducing the read disturbance time by half. Results from a Monte Carlo HSPICE simulation using the parameters of a 45-nm industry-compatible model show that the HPWRD scheme produces a three-order improvement in the RDM without sacrificing the SM, speed, or energy efficiency, at the cost of an increased area overhead of 4.12% for a subarray size of 128 $\times$ 16.

Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual $V_{\mathrm {ref}}$ sensing scheme (DVSS) that selectively uses an optimal $V_{\rm {ref}}$ between $V_{\rm {ref+}}$ and $V_{\rm {ref-}}$ is proposed. This scheme is tolerant to process variations, and can be used as a spin-transfer-torque random access memory. Because of no additional sensing stage, the offset-tolerant sensing is achieved without sacrificing the performance. The optimal $V_{\rm {ref}}$ is selected after fabrication, and the calibrated switch control bit, which contains $V_{{\rm {ref}}}$ selection information, is stored permanently in an on-chip nonvolatile latch. Monte Carlo HSPICE simulation results, using an industry-compatible 45-nm model parameters, show that the proposed DVSS achieves a read yield of 98.24% for 32 Mb (6.1 sigma) with $2\times $ faster sensing speed and $1.5\times $ lower read energy per bit compared with the state-of-the-art offset-tolerant sensing scheme.

A highly tunable oscillator using magnetic tunnel junctions (MTJs) has been developed through integration with CMOS ring oscillators. MTJs are used to replace the pMOS transistors in a typical CMOS inverter fabricated in 40-nm CMOS. The hybrid MTJ-CMOS devices exhibit a voltage-controlled oscillator gain of 300–500 MHz/V and are tunable with respect to both voltage and magnetic field.

Resistive nonvolatile memory (NVM) devices such as spin transfer torque random access memory (STT-RAM) and resistive random access memory are considered to be leading candidates for next-generation memory devices. With technology scaling, the sensing margin (SM) of the resistive NVM devices is significantly degraded because of increased process variation and decreased read current. In this brief, we propose an offset-canceling dual-stage sensing circuit (OCDS-SC) that has the two major advantages of offset voltage cancelation and double SM. Monte Carlo HSPICE simulation results using a 45-nm technology for STT-RAM show that the OCDS-SC achieves a read access yield of 99.93% for 32 Mb (6.6 sigma) with a read current of 15 $\mu\mbox{A}$ and sensing time of 3.4 ns.

In order to enable the spin-transfer torque (STT) magnetoresistive random access memory technologies, it is essential to control the thermal budget, perpendicular magnetic anisotropy, and magnetic damping parameter of perpendicular magnetic tunnel junction (pMTJ) thin films. This paper demonstrates the enhancement of pMTJ free layer (FL) properties through selective engineering of capping materials placed between a CoFeB FL and the top electrode. By introducing a capping layer of Mg or MgO, thermal budget and tunneling magnetoresistance (TMR) ratio are significantly improved over the conventional FL schemes due to reduced atomic intermixing at interfaces. In full-stack pMTJ films, thin Mg above the FL enables the TMR above 170% after 400 °C annealing. Capping via MgO increases the interface anisotropy, allowing for the use of thicker CoFeB FLs with magnetic damping constants as low as 0.003. We discuss the implications of these capping layer improvements and suggest that Mg and MgO show the potential for optimizing the FLs with high-thermal budget and good STT efficiency.

The scaling of STT-MRAM for deeply scaled nodes (e.g. sub-10 nm CMOS) requires low resistance-area-product (RA) magnetic tunnel junctions (MTJs) to contain switching voltage (V c ) and to assure high endurance. In contrast to various reports, we demonstrate systematic engineering of low-RA MTJs without trading off key device attributes and remarkably, with higher barrier reliability. The MTJs integrate an ultra-thin synthetic antiferromagnetic layer (tSAF) with a Co/Pt pseudo-alloy pinned layer. By reducing RA from 10 to 5 Ωµm2, significantly reduced V c and reliable switching at 5 ns have been achieved. Furthermore, the breakdown voltage (V BD ) has been improved. The results suggest that the tunability of MTJ is extended to sub-10 nm CMOS for high-performance and high-reliability MRAM.

MRAM, specifically, perpendicular spin-transfer-torque (STT) MRAM, has reached a stage to serve early adopters. With its unique attributes and tunability, MRAM can create desirable system differentiations which were not possible due to inherent limitations of various memories. MRAM is poised for a unified memory subsystem that can revamp the architectures of emerging ultra-low-energy systems such as Internet-of-Things (IOT) and wearable devices. Furthermore, MRAM has a potential to transform computing-centric architectures at more advanced nodes.

Spin-transfer torque random access memory (STT-RAM) is a promising candidate for universal memory due to its speed, scalability, and non-volatility. A wide range of write speeds from $1$ to $100\,\mathrm {ns}$ have been reported for STT-RAM. As the storage element of an STT-RAM cell, the switching current of magnetic tunnel junction (MTJ) is inversely proportional to the write pulse width. In this work, we propose a methodology to design STT-RAM for different optimization goals such as read performance, write performance, and write energy by leveraging the trade-off between write current and write time of MTJ. To enable STT-RAM design in advanced technology nodes beyond 22 nm, we model perpendicular MTJ (PMTJ) as the storage element and FinFET as the access transistor. Our study shows that reducing write pulse width will harm read latency and energy. It is observed that “sweet spots” of write pulse width which minimize the write energy or write latency of an STT-RAM macro may exist. The optimal write pulse width depends on both the device and the architecture specifications. The impact of process variations including the MTJ and the FinFET access transistor are also analyzed.

As technology node shrinks, spin-transfer-torque random access memory (STT-RAM) has become a promising memory solution owing to its great scalability. However, the increase in process variation and decrease in the supply voltage result in the degradation of the read yield; thus, achieving the target read yield is an important issue in a deep-submicrometer technology node. In this paper, we propose a latch offset cancellation sense amplifier (LOC-SA) that cancels the latch offset with a compact area by merging the sensing circuit, latch sense amplifier, and write driver. By virtue of the latch offset cancellation characteristic, the voltage developing time can be significantly saved, leading to sensing-speed improvement. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the LOC-SA satisfies a target read yield of six-sigma (96.74% for 32 Mb) with more than 2 $\times$ faster sensing speed, 1.12 $\times$ lower read energy, and 1.13 $\times$ smaller area when compared with the best value of design parameters of other sense amplifiers.

As process technology scales down, sensing becomes difficult during read operations because the supply voltage, i.e., VDD, decreases and the process variation increases. Thus, a high enough sensing yield cannot be obtained with a conventional sensing circuit in deep submicron process technology. In this brief, a split-path sensing circuit is proposed to achieve a large enough sensing margin by using a variable reference voltage. The proposed sensing circuit is verified using Monte Carlo HSPICE simulation with industry-compatible low-leakage 45-nm model parameters. The proposed circuit has a sensing yield of 99% for 1-Mb memory with a sensing time of 1 ns and a sensing yield of 99% for 32-Mb memory with a sensing time of 3 ns.

We present a comprehensive device and scalability validation of STT-MRAM for high performance applications in sub-10 nm CMOS by providing the first statistical account of barrier reliability in perpendicular magnetic tunnel junctions (pMTJs) from 70 to 25 nm diameter in 1 Gbit arrays. We have experimentally investigated the time-dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, duty-cycle, and temperature. A large write-to-breakdown voltage window of > 1 V (> 20 σavg) was measured and a long time-to-breakdown was projected (> 1015 cycles) for 45 nm pMTJs, guaranteeing practically unlimited write cycles. We also reveal a dramatic enhancement of barrier reliability in conjunction with pMTJ size scaling down to 25 nm diameter, further widening the operating window at deeply scaled nodes.

A spintronic integrated circuit (IC) is made of a combination of a semiconductor IC and a dense array of nanometer-scale magnetic tunnel junctions. This emerging field is of growing scientific and engineering interest, owing to its potential to bring disruptive device innovation to the world of electronics. This technology is currently being pursued not only for scalable non-volatile spin-transfer-torque magnetoresistive random access memory, but also for various forms of non-volatile logic (Spin-Logic). This paper reviews recent advances in spintronic IC. Key discoveries and breakthroughs in materials and devices are highlighted in light of the broader perspective of their application in low-energy mobile computing and connectivity systems, which have emerged as leading drivers for the prevailing electronics ecosystem.

Recently, a magnetic tunnel junction (MTJ), which is a strong candidate as a next-generation memory element, has been used not only as a memory cell but also in spintronics logic because of its excellent properties of nonvolatility, no silicon area occupation, and CMOS process compatibility. One of the representative research areas for the spintronics logic is the zero standby leakage retention flip-flop. Conventional zero standby leakage retention flip-flops have several problems, including difficulty in design optimization among the C-Q delay, sensing current, and process variation tolerance, and the insufficient write current. In this paper, a new MTJ based retention flip-flop is presented to solve these problems. The proposed retention flip-flop is designed using industry-compatible 45-nm process technology model. The proposed retention flip-flop achieves a 41.58% reduced C-Q delay and a 67.53% lowered sensing current with a 1.06% increased area compared to the previous retention flip-flop.

As the memory density increases for the big-data processing, the sensing speed is degraded because of the increased parasitic capacitive load. Thus, the equalization (EQ) scheme that is capable of improving the sensing speed has now become essential. This paper examines the effectiveness of EQ scheme on the sensing speed of offset-canceling dual-stage sensing circuit (OCDS-SC) in terms of cells per bit line (CpBL). The simulation results show that the OCDS-SC with EQ scheme achieves 3 times faster sensing time than that without EQ scheme in case of CpBL of 128. Additionally, the EQ scheme becomes more effective for reducing the sensing time according to the increase in the number of CpBL.

As the technology node scales down, a sufficient read current that is capable of achieving a target read yield cannot be used because of the read disturbance problem in spin-transfer-torque random access memory (STT-RAM). As an alternative method, increasing the sensing circuit (SC) area is generally considered because it can reduce the threshold voltage (Vth) variations. However, the increased SC area can adversely reduce the read yield due to the increased load capacitance. The effects of the increased area on read yield can be different according to the SCs because of their own characteristics. In this work, the trends of read yield according to the area are analyzed for two representative SCs, and the areas of two SCs are optimally designed to have high read yield.

The emerging spin-transfer torque magnetic random-access memory (STT-RAM) has attracted a lot of interest from both academia and industry in recent years. It has been considered as a promising replacement of SRAM and DRAM in the cache and memory system design thanks to many advantages, including non-volatility, low leakage power, SRAM comparable read performance and read energy consumption, higher density than SRAM, better scalability than conventional CMOS technologies, and good CMOS compatibility. However, the disadvantages of STT-RAM, such as higher write energy and longer write latency than SRAM, also bring design challenges. This paper introduces state-of-the-art architectural approaches to adopt STT-RAM in the cache and memory system design by taking advantage of the opportunities brought by STT-RAM as well as overcoming the challenges.

The conventional magnetic tunneling junction MTJ-based non-volatile D flip-flop NVDFF has a slow D-Q delay and a tradeoff between its D-Q delay and its sensing current. In addition, a sufficient write current cannot be obtained with the core device, since two MTJs exist in the write path and a write current degradation problem occurs due to the precharge transistors. The proposed MTJ-based non-volatile semidynamic flip-flop NVSDFF has a semidynamic structure that ensures a fast D-Q delay and separates the sensing circuit from the D-Q signal path to reduce the sensing current without affecting the D-Q delay. The proposed NVSDFF also provides a sufficient write current by merely using the core device, since only one MTJ exists in the write path. In addition, the head switch, which is added to remove the write current degradation problem, further reduces the sensing current. Thus, the proposed NVSDFF has a higher read disturbance margin than the previous NVDFF with an IO device. The HSPICE simulation results with the industry-compatible 45nm model parameter show that the D-Q delay in the proposed NVSDFF is 50.5% of that of the previous NVDFF with an IO device, and the sensing current, 32.3%. In the proposed NVSDFF, the read disturbance margin is 15.9% larger than in the previous NVDFF with an IO device, and the area is 17.8% smaller. Copyright © 2012 John Wiley & Sons, Ltd.

Novel memory programming methods and corresponding memory structures are presented in this paper. Unlike conventional memory programming, this programming technique does not require deterministic switching of memory elements. This technique explicitly exploits the probabilistic switching characteristics of memory elements such as spin-transfer torque magnetic tunnel junction (STT-MTJ) to reduce programming power and delay. This technique also allows multilevel cell (MLC) spin-transfer torque magnetoresistive random access memory (STT-MRAM) to be fabricated with existing STT-MTJ fabrication processes, thus making high capacity STT-MRAM chips readily achievable. The optimal STT-MTJ switching probabilities are given in this paper for reaching minimum programming delay, power, and iteration. Moreover, this paper proves, by applying probabilistic programming to existing STT-MTJs, both programming delay and power can be reduced to levels beyond the reach of conventional deterministic programming. Furthermore arbitrarily small programming bit error rate (BER) can be accomplished in theory using probabilistic programming without much penalty on average programming delay and power. On the contrary, deterministic programming always presents finite programming BER, which is expensive to reduce in terms of programming power and delay. The MLC capability of STT-MTJ clusters has also been confirmed using fabricated STT-MTJ devices. The major circuitries for implementing probabilistically programmed MLC STT-MRAM are also presented in this paper.

This paper demonstrates the co-optimization of all critical device parameters of perpendicular magnetic tunnel junctions (pMTJ) in 1 Gbit arrays with an equivalent bitcell size of 22 F2 at the 28 nm logic node for embedded STT-MRAM. Through thin-film tuning and advanced etching of sub-50 nm (diameter) pMTJ, high device performance and reliability were achieved simultaneously, including TMR = 150 %, Hc > 1350 Oe, Hoff 1012 write cycles). Reliable switching with small temporal variations (< 5 %) was obtained down to 10 ns. In addition, tunnel barrier integrity and high temperature device characteristics were investigated in order to ensure reliable STT-MRAM operation.

In this paper, we first analyze the efficiency of importance sampling (IS) method in spin transfer torque random access memory (STT-RAM) design with industry-compatible model parameter. Commonly used normal fitting method cannot estimate the yield accurately unless an output distribution follows the Gaussian distribution. The efficiency of IS method is significantly degraded when industry-compatible model parameters are used because most variables affected by process variation are not controllable. With industry-compatible 45-nm model parameters, Monte Carlo HSPICE simulation results show that the required number of simulations to satisfy error rate less than 5% should be greater than 50,000.

BACKGROUND Toll-like receptor 4 (TLR4) is the main immune molecule that recognizes lipopolysaccharide from gram-negative bacteria. Single-nucleotide polymorphisms (SNPs) in the TLR4 gene that impair lipopolysaccharide recognition may influence gram-negative bacterial infections after liver transplantation. METHODS TLR4 D299G and T399I SNPs were assessed in a cohort of 706 liver transplant recipients and were associated with the clinical characteristics and outcome of gram-negative bacterial infections. Cox proportional hazard model was performed to determine covariates associated with outcomes after gram-negative bacterial infections. RESULTS Of 706 patients, there were 108 with microbiologically confirmed gram-negative bacterial infections, 135 with clinically suspected but not confirmed infections, and 463 patients without gram-negative bacterial infections. The proportions of TLR4 D299G (5/108 [4.6%] vs. 32/463 [6.9%]; P=0.39) and T399I SNPs (19/108 [17.6%] vs. 68/463 [14.7%]; P=0.45) did not differ between those with or without microbiologically confirmed gram-negative bacterial infections. Female gender (odds ratio 2.30, 95% confidence interval [CI]1.50-3.53; P

Infectious diseases are important causes of morbidity and mortality in solid organ transplant (SOT) recipients. While potent immunosuppressive agents have dramatically reduced the incidence of allograft rejection, these agents have also rendered patients highly susceptible to common and opportunistic infections.(1) Infections during the early period after SOT are often donor- or recipient-derived or are associated with surgical and nosocomial complications. Various opportunistic infections occur later, at 1–6 months after SOT, when the impact of potent immunosuppression is most intense. Risk of infection generally diminishes 6 months after SOT, because immunosuppressive agents are tapered to minimal levels in SOT recipients with satisfactory allograft function.(1) Liver transplantation is a technically complex procedure that is performed in a potentially-contaminated environment within the abdominal cavity. Many liver transplant candidates are in an extremely morbid condition at the time of liver transplantation.(2) Intra-abdominal infections and peritonitis are the predominant sites of post-operative infections, and these generally occur during the first 2 months after liver transplantation.(2–4) In one study, over 50% of intra-abdominal infections and peritonitis were accompanied by bacteremia.(2) These infections are often associated with poor immediate and long-term outcomes. Courses of antibacterial therapy are therefore used commonly after liver transplantation, and their efficacy is dependent on the microbiology of such infections. Occasionally, the microbiology of bacteremia may not be defined particularly in patients who received empiric courses of antimicrobial therapy prior to obtaining specimens for bacterial cultures. We therefore aimed to assess the spectrum of bacteremia in relation to its onset after liver transplantation. In the process, we compared the clinical and microbiologic characteristics of patients who developed early-onset (defined as ≤ 2 months) and late-onset (> 2 months) bacteremia after liver transplantation.

Magnetoresistive random access memory (MRAM) is a leading candidate for future memory applications because it may provide compelling advantages by combining desirable attributes of SRAM, DRAM, and Flash. Process technology has recently scaled down to the nano-meter regime, which accordingly has resulted in lowering supply voltage, increasing short channel effect, and rapidly increasing process variation. MRAM is also affected by technology scaling, which significantly reduces the sensing margin. In this paper, several circuit design parameters, such as supply voltage, transistor size, and transistor gate voltage in the sensing circuit, are evaluated to discover the root causes of reduced sensing margin with technology scaling. The lowered supply voltage and lowered output resistance of the transistor, which occurs with technology scaling, are verified as the root causes of reduced sensing margin. It is also shown that increased process variation due to technology scaling aggravates the problem. A high supply voltage with power gating combined with optimized transistor size and gate voltage, and a power gating scheme using an IO device with an IO voltage are suggested as effective design solutions for reliably increasing the sensing margin in the presence of process variation. Copyright © 2010 John Wiley & Sons, Ltd.

Spin-transfer-torque magnetoresistive random access memory (STT-MRAM) has been considered a promising technology for future mobile system-on-chip memories due to negligible static leakage power, high-speed read/write operations, and unlimited read/write endurance. In this paper, we address key challenges and recent advances for enabling embedded STT-MRAM on a deeply scaled CMOS logic platform.

Commercializing spin-transfer-torque magnetic random access memory (STT-MRAM) requires thorough investigation of magnetic tunnel junctions (MTJs) at temperature corners. In this paper, high-temperature behaviors of MTJs are investigated in conjunction with temperature-dependent transistor characteristics in order to ensure reliable high-temperature operation of STT-MRAM.

Back-end-of-the-line (BEOL) interconnect becomes a limiting factor to circuit performance in scaled complementary metal-oxide-semiconductor design. To accurately extract its paratactic capacitance for circuit simulation, compact models should be scalable with wire geometries and should capture the latest technology advances, such as the air gap and Cu diffusion barrier. This paper achieves these goals based on the distribution of the electric field in on-chip BEOL structures. By decomposing the electric field into various regions, the proposed method physically solves each basic capacitance component into a closed-form solution; the total ground and coupling capacitances are then the sum of all related components. Such a component-based approach is convenient in incorporating new interconnect structures. Its physics basis minimizes the complexity and the error in a traditional model fitting process. Compared with Raphael simulations at the 45-nm node, the new compact model accurately predicts the capacitance value, even in the presence of the air gap and diffusion barrier, covering a wide range of BEOL dimensions. The complete set of equations will be implemented at http://www.eas.asu.edu/~ptm.

The emerging field of spintronics has the potential to bring game-changing opportunities to nanoelectronic technologies far beyond its traditional contribution to mass storage applications such as hard disk drives. The value proposition is timely since the dominant semiconductor industry is in pursuit of “More-than-Moore” to extend the technology roadmap or to create functional diversifications through enhanced system platforms. This article overviews a promising spintronic device in conjunction with recent breakthroughs in tunnel magnetoresistance and spin-transfer-torque magnetization switching.

A global reference-circuit (RC), which means one RC is shared with many sensing circuits (SC), is being considered for high-bandwidth STT-RAMs because of the low power consumption and small area characteristic. However, using the global RC for high-bandwidth STT-RAMs causes a droop effect and coupling noise effect, leading to the significant performance degradation. Thus, the validity of using the global RC should be identified. In this paper, the local RC and various global RCs are introduced, and compared in aspects of area, sensing time, and power consumption. By classification of the merits and demerits of various RCs, we present the following requirements of proper RC for high-bandwidth STT-RAMs: 1) small area, 2) no performance degradation, 3) low power consumption, and 4) process variation tolerant reference signal generation.

Spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is made of a combination of semiconductor integrated circuits (IC) and a dense array of nanometer-scale magnetic tunnel junctions (MTJ). This emerging memory is of growing technological interest due to its potential to bring disruptive device innovation to the world of electronics. STT-MRAM is capable of providing high speed, unlimited endurance, and nonvolatility simultaneously, which is often recognized as a unique advantage over conventional and other emerging memories. While the technology is at an early stage and evolving in multiple platforms, STT-MRAM is particularly compelling as an embedded memory for system-on-chip (SOC). STT-MRAM can be integrated into SOC without altering baseline logic platforms both in process and in design. This chapter overviews key device and circuit subjects from the perspective of co-designing logic and MTJ.

As technology node scaling, FinFET becomes the substitution for planar MOSFET due to several merits of FinFET such as superior gate controllability, large on-current, and low variability. For the reasons, using FinFET as access transistor of spin-transfer-torque random access memory (STT-RAM) cell should be analyzed. This paper compares using planar MOSFET and FinFET as access transistor of STT-RAM cell and concludes which device is more proper solution for high write and read yields.