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In recent year, the thermal effect has become a critical issue on the operation of memory cell. As heating time or temperature increases, the performances of memory cells are degraded due to its low thermal stabilities. Therefore, processes working at low temperature are necessary not to hurt the thermal stability. In this paper, we introduced LTSOC (Low Temperature Spin-On Carbon), which is believed to minimize the thermal loads because its cross-linker works at low temperature. Also, it would be important to fulfill the needs for the other properties of SOC like filling ability and etching resistance. So, we verified all these basic characteristics with proper resist and etching processes by getting good final pattern profile. As a result, LT-SOC is suggested for etching barrier without affecting on cell operation of memory devices.

Background: Simultaneous liver and kidney transplants have proved to be a favorable treatment for combined renal and hepatic end-stage diseases. However, it is extremely difficult to find a simultaneous liver and kidney donor in Korea due to the narrow requirements. This study had three aims: to explore the therapeutic experience of simultaneous liver and kidney transplants in Seoul National University Hospital (SNUH), to compare the overall survival outcome between simultaneous liver and kidney transplants and liver transplants alone in patients with liver and renal failure, and to determine the indications for simultaneous liver and kidney transplants. Methods: The clinical data of 8 simultaneous liver and kidney transplants at SNUH from November 2004 to October 2010 were retrospectively studied. Indications for simultaneous liver and kidney transplants, patient and graft survival, and the causes of death were analyzed and compared with 5 liver transplants alone performed on patients experiencing liver and renal failure. Results: The clinical characteristics of the recipients for simultaneous liver and kidney transplants and liver transplants alone were similar with regards to age, renal function, and the Model for End-Stage Liver Disease (MELD) score (all P>0.05). One patient died at 15 months after simultaneous liver and kidney transplants due to HBV related HCC recurrence, and three patients died at 2, 3, and 21 months after liver transplants due to ARDS, bleeding, and hepatic failure, respectively. Only one liver graft loss in simultaneous liver and kidney transplant cases occurred on POD 3 due to primary non-function. The outcome analysis demonstrated a superior overall survival in simultaneous liver and kidney transplants recipients compared with recipients of only liver transplants (P=0.041). Conclusions: Simultaneous liver and kidney transplants showed a superior outcome in patients with end-stage liver disease and chronic renal failure compared with liver transplants alone. The allocation criteria of simultaneous liver and kidney transplants in Korea should be changed to expand its indications.

As EUV reaches high volume manufacturing, scanner source power and reticle defectivity attract a lot of attention. Keeping a EUV mask clean after mask production is as essential as producing a clean EUV mask. Even though EUV pellicle is actively investigated, we might expose EUV masks without EUV pellicle for some time. To keep clean EUV mask under pellicle-less lithography, EUV scanner cleanliness needs to meet the requirement of high volume manufacturing. In this paper, we will show the cleanliness of EUV scanners in view of mask particle adders during scanner exposure. From this we will find several tendencies of mask particle adders depending on mask environment in scanner. Further we can categorize mask particle adders, which could show the possible causes of particle adders during exposure in scanners.

In this paper, we will present the experimental comparison results on contact holes (CHs) and pillars patterning in EUV lithography with several candidate processes. Firstly, we have compared the normalized image log-slope (NILS), local critical dimension uniformity (LCDU) and dose-to-size (DtS) with respect to positive tone imaging (PTI) and negative tone imaging (NTI) process by EUV stochastic simulation. From the simulation results, we found that NTI process has higher absorbed photon density that can reduce the DtS and the LCDU of pillars pattern is improved with higher NILS compared to CHs patterning with similar DtS. So we have experimentally evaluated the pillars patterning process with 0.25NA EUV scanner system and compared the process margin, LCDU and DtS with the same parameters of the CHs pattering process. Further, we have demonstrated the CHs patterning with reverse process from pillars by using the dry development rinse process (DDRP). Different to the simulation results, the experimental LCDU results of pillars pattern and CHs pattern by DDRP show worse values comparing with the reference resist CHs pattern. In order to analyze these results, we have investigated the effect of flare, target CD, PR thickness and mask stack of the experimental conditions. Furthermore, we have evaluated the pillar patterning with NTD resist and by DDRP.

EUV lithography (EUVL) is the most promising technology to extend the resolution limit, and is expected to be used if the enough source power is delivered and mask defect mitigation method is developed. However, even in that case, the number of EUV steps will be restricted by its high cost, and ArF immersion will still take a major role in the chip manufacturing. Therefore, it is important to check and improve the mix-match overlay (MMO) between EUV and ArF immersion steps. In this paper, we evaluate EUV MMO with ArF immersion system by comparing with dedicated chuck overlay (DCO). The major contributors on MMO are random and field component from overlay analysis. MMO is expected to be below 3nm by applying 18para CPE TM (correction per exposure) and RegC TM (Registraion error correction). We consider High oder CPE TM need to be developed for further improvement.

Experimental local CD uniformity (LCDU) of the dense contact-hole (CH) array pattern is statistically decomposed into stochastic noise, mask component, and metrology factor. Each component are compared quantitatively, and traced after etching to find how much improvement can be achieved by smoothing. Etch CDU gain factor is defined as the differential of etch CD by resist CD, and used to estimate etch CDU on resist CDU. Stochastic noise has influenced on not only LCDU but also local placement error (LPE) of each contact-hole. This LPE is also decomposed into its constituents in the same statistical way. As a result, stochastic noise is found to be the most dominant factor on LCDU and LPE. Etch LCDU is well expected by Etch Gain factor, but LPE seems to be kept same after etching. Fingerprints are derived from the repeating component and the boundary size for excluding proximity effect in analysis is investigated.

ASML NXE3100 has been introduced for EUV Pre-Production, and ASML NXE3300 for High Volume Manufacturing will be installed from this year. EUV mask defect control is the one of the concerns for introducing EUVL to device manufacturing, for current EUV mask defect level is too high to accept for device volume production. EUV mask defects come from mask blank, mask process and mask handling. To have reduced mask defect level, quality control of blank mask, optimization of EUV mask process and improvement of EUV mask handling need to be ready. In this paper, we analyze printed defects exposed from EUV full field mask at NXE3100. For this analysis we trace mask defects from mask to wafer printing. From this we will show current EUV mask’s defect type and numbers. Acceptable defect type, size and numbers for device manufacturing with EUVL will be shown. Through investigating printing result of natural ML defects, realistic level of natural ML defects will be shown.

Double patterning lithography has been one of the candidates for sub-40nm patterning era, and has a lot of process issues to be confirmed. Last year, we presented the issues in double patterning lithography with a real flash gate pattern. Process flow was suggested and CD uniformity due to overlay was analyzed. And the layout decomposition and the two types of double patterning of positive and negative tone were studied with 1-dimensional pattern. In this paper, the implementation to DRAM patterns is examined, which consist of 2-dimensional patterns. Double patterning methods and the selection of their tone for each layer are studied, and the difficulties from the randomness of core pattern are also considered. As a result, DRAM patterns have more restrictions on the double patterning method and selection of tone, and the aggressive layout decomposition should be designed to solve the difficulty in core patterning. Therefore, 37nm DRAM layout can be patterned and the overlay control and cost still remain as dominant obstacles.

For the first time, this paper presents the results of successful integrations of Cu wiring into a production 512 Mb/90 nm design-rule stacked capacitor and recessed gate DDR (double data rate) DRAM technology, focusing on the effects of Cu integration on DRAM performance, yield, refresh time, and wafer-level reliability. 2 levels Cu interconnect (Ml single damascene and M2 dual damascene) and CVD low-k (FSG) materials have been implemented. Both the reduction in parasitic capacitance and line resistance were found to improve the operation speed of DRAM. No degradation was observed in view of normalized refresh time and yield with Cu wiring. The reliability issues with Cu integration to DRAM were systematically evaluated. In conclusion, this study demonstrates that the Cu wiring is fully compatible with the conventional DRAM and will be expected to meet the requirements of high-performance and high-speed advanced DRAM beyond sub-50 nm node.

There have been imposed quite incompatible requirements on lithographic simulation tool for OPC, that is it should be enough accurate and enough fast. Though diffused aerial image model (DAIM) has achieved these goals successfully, rapid transition of lithography into very low k1 and sub-resolution regime makes it very difficult to meet these goals without loss of any of speed or accuracy. In this paper we suggested new modeling method of resist process which is called heterogeneous diffusion of aerial image. First, various examples of CD discrepancy between experiment and simulation with DAIM are suggested. Then the theoretical background of new model is explained and finally CD prediction performance of new model is demonstrated in 60nm 0.29k1 patterning of real DRAM devices. Improved CD prediction capability of new model is observed in various critical patterning of DRAM.

Double patterning lithography is very fascinating way of lithography which is capable of pushing down the k1 limit below 0.25. By using double patterning lithography, we can delineate the pattern beyond resolution capability. Target pattern is decomposed into patterns within resolution capability and decomposed patterns are combined together through twice lithography and twice etch processes. Two ways, negative and positive, of doing double patterning process are contrived and studied experimentally. In this paper, various issues in double patterning lithography such as pattern decomposition, resist process on patterned topography, process window of 1/4 pitch patterning, and overlay dependent CD variation are studied on positive and negative tone double patterning respectively. Among various issues about double patterning, only the overlay controllability and productivity seemed to be dominated as visible obstacles so far.

Though speculation on immersion is ignited by the possibility in realization of hyper NA lithography system which will have NA> 1.0, it is thought that the immersion era might come earlier even in ≤1.0 NA regime because of great benefit in increasing DOF. On the other hand, questions are still laid on maturity or reliability issues such as lens contamination, bubble defects, overlay control and so forth. The main subject of this paper is how to find the appropriate time for introduction of immersion. Basic performance of immersion lithography in 80nm DRAM is compared with that of conventional dry lithography through experiment and simulation. Result of simulation is quite well matched with that of the experiment, and therefore we can investigate the limit of conventional dry lithography based on the simulation results.60nm node might be remained as a last regime for conventional dry lithography by virtue of polarized illumination, and we can expect the shoreline beyond there.

512Mbit DRAM with 70 nm design rule was tailored using 0.31k1 ArF lithography technologies. Of the critical mask layers, four pattern layouts were demonstrated: brick wall, line/space, contact and line/contact patterns. For the sake of cost reduction, the conventional technologies were used. Results has shown that SLR (Single-Layer Resist) process, half-tone PSM and the conventional illuminations had a potential of manufacturing 70 nm DRAM. However, it was found that brick wall patterns had asymmetrical shape and total CD uniformity was out of target raging 9.2 nm through 16.3 nm depending mask layouts. We prospect that higher contrast resist and more elaborate resist process will address these problems sooner or later. In case the immersion lithography is not ready around the right time, the feasibility of 0.29k1 ArF lithography was studied through simulation and test, which represented that 0.29k1 technologies were likely to be applied for the development of 60 nm DRAM with the aid of RETs (Resolution Enhancement Technologies) including customized illumination and new hard mask process.

To accomplish minimizing feature size to sub 60nm, new light sources for photolithography are emerging, such as F2(157nm), and EUV(13nm). However, these new lithographic technologies have many problems to be solved for real device production. In case of F2 lithography, pellicle issue makes it difficult to use of F2 source in mass production. In case of EUV, light source and mask fabrication issues must be solved for real device application. For these reasons, instead of new light sources, extension of dry ArF lithography has been studied for sub 70nm device production by using Resolution Enhancement Technology (RET) such as using high NA tools, off axis illumination, and phase shift mask. Recently, a new technology called ArF immersion lithography is emerging as a next generation lithography. The first problem of this technology is contamination issues that come from the dissolution of contaminants from the photoresist to the immersion liquid. The second is optical problem that comes from the using hyper NA system. To solve these two problems, we have developed top antireflective coating (TARC) material. This TARC material can be coated on resist without damage to the resist property. In addition to, this TARC material is easily developable by conventional 2.38 wt% TMAH solution. The reflective index of this TARC is adjusted to 1.55, so it can act as an antireflective material. To this TARC material for immersion, quencher gradient resist process (QGRP) was applied also. As a result, we could improve resolution and process margin. However, some of resists showed defects that were generated by this TARC material and QGRP. To solve this defect problem, we introduced buffer function to the TARC material. Thanks to this buffer function, we could minimize defects of resist pattern in immersion lithography.

Various enhancement techniques such as alternating PSM, chrome-less phase lithography, double exposure, etc. have been considered as driving forces to lead the production k1 factor towards below 0.35. Among them, a layer specific optimization of illumination mode, so-called customized illumination technique receives deep attentions from lithographers recently. A new approach for illumination customization based on diffraction spectrum analysis is suggested in this paper. Illumination pupil is divided into various diffraction domains by comparing the similarity of the confined diffraction spectrum. Singular imaging property of individual diffraction domain makes it easier to build and understand the customized illumination shape. By comparing the goodness of image in each domain, it was possible to achieve the customized shape of illumination. With the help from this technique, it was found that the layout change would not gives the change in the shape of customized illumination mode.

A multilevel interconnection technology using an HDP-CVD SiOF film is demonstrated for 0.25 /spl mu/m LSI devices. A stable HDP-SiOF film is realized as the intermetal dielectric (IMD). When HDP-SiOF has Si-F/sub 2/ bonds and silicon dangling bonds, the film stress changes during thermal stressing. This unstable HDP-SiOF causes deformation of the metal underlayer due to the film stress change. The device performance with a stable HDP-SiOF film is improved, showing a 12% reduction in wiring capacitance. In addition, gate oxide leakage characteristics are also superior to those of conventional undoped silicate glass (USG). The stable HDP-SiOF film has been successfully applied as an IMD layer for 0.25 /spl mu/m LSI devices.

Lately, photolithography is seen as the bottleneck to sub-0.1 /spl mu/m patterning. Namely, the miniaturization of the design rule pushes the pattern sizes in the peripheral region as well as in the cell region into the resolution limit of exposure tools. Although it is common to use single exposure for lithographic layer formation, an ArF double exposure technique (DET) strategy, based on manual OPC and an in-house simulation tool, HOST (Hynix OPC simulation tool), is suggested as a possible exposure method for overcoming the limit and its results on wafer are shown. The in-house simulation tool used in this paper can predict the wafer pattern and process margin of a lithographic layer and shows good validity in the ArF process.

Recently a 130 nm design rule device has been attempted with OAI (Off Axis Illumination) and PSM (Phase Shift Mask) in KrF, and is thought to be the nodal point of KrF and ArF lithography. However, the ArF process has not yet matured, so an extension of KrF is considered for sub-120 nm patterning. The process margins, especially exposure latitude, are investigated on the basis of the amount of 1st order light into the entrance pupil. At first, 120 nm patterns were tried for the annular condition on the basis of that result. A modified dipole was suggested for sub 120 nm patterning. For design of the dipole, asymmetry in X and Y directions was taken into consideration. The availability of a modified dipole is evaluated for 110 nm dense lines and 130nm or less device patterns.

As the pattern size becomes smaller, double or multi exposure is required unless the epochal solutions for overcoming the limits of present lithography system do appear or are discovered. ArF DET (double exposure technology) strategy based on manual OPC with in-house simulation tool, HOST (Hynix OPC simulation tool), is suggested as a possible exposure method to extend the limitation of current lithography. HOST requires no additional procedures and separate layout optimizations of each region in terms of OPC are enough. Furthermore, it is possible to change illumination condition of each region and the overlap between two regions with ease. The results from the simulation are pattern size and profile of each condition according to the defous and misregistration. 0.63 NA ArF Scanner and Clariant resist is used for wafer process. The resist was coated on Clariant organic BARC using 0.24 um thickness. Dipole illumination for cell region and annular illumination for peripheral region are used. Cell region contains 0.20 um pitch duty pattern and peripheral region 0.24 um pitch duty pattern. The boundary of two regions is investigated in view of validity of stitching itself. The layout of reticles used as the cell and peripheral region are optimized by OPC, respectively and then, additional OPC was treated to the boundary, i.e., stitching area to compensate the cross term of the boundary caused by separate and independent optimization with OPC in the cell and the peripheral regime. The final patterns were acquired by defining the cell at first and the peripheral region secondly with different defocus and registration in respect to the cell. The actual data on wafer are presented according to defocus and one region's overlay offset relatively to the other region. And the outstanding matching between simulation results and in-line data are shown. Lithography process window for stable patterning is thoroughly investigated in view of depth of focus, energy latitude, registration between two stitched regions and stitching itself in the boundary. It is found from the experiment that total DOF of DE (double exposure) is 0.5 um and the total EL of DE is 10.0% in this paper. At present, it is very difficult to ensure stable process margin for the sub-0.10 um patterning. But there is a promising technology called stitching with special optimization. In addition, this technology will be nominated as an eternal candidate process whenever our lithography is in the adversity at the limits of his days.

This paper describes the effect of the mask errors such as mask critical dimension (CD) variation, phase and transmission error of attenuated phase shifting mask (att-PSM) on wafer CD in ArF lithography and also analyzes these errors quantitatively. Mask CD requirement using ELF and MEF is estimated firstly and mask CD should be controlled within about 7nm assuming O.7ONA ArF system with 1% illumination uniformity. Transmission error induces larger CD variation than phase error. However, phase error should be considered otherwise in that it reduces depth of focus (DOF). To control DOF degradation less than 10% in case of O.l4um and O.l6um isolated contact hole(C/H), the phase should be controlled within the range of Considering O.l4um isolated contact hole, transmission error of occupies 10% of CD tolerance. Finally, the budget of these factors are calculated in view of total wafer CD variation quantitatively except lens aberration, resist process, and etc. To reduce wafer CD variation, we should control mask CD more tightly.

This paper describes that attenuated phase shift masks (APSM) improve process margin compared to binary mask (BIM) in KrF and ArF lithography. We present the real problems to occur in the mask fabrication, process and mask error factor (MEF). As a result, sub-120nm cell patterns were delineated with 8% exposure latitude (EL) and ~0.6 ?m local depth of focus (LDOF) using 0.70NA KrF and APSM. The performance of ArF lithography (NA=0.63) shows the similar process margin with 10% EL and -0.6 ?m LDOF. Using APSM, we could obtain 14.4% EL and -0.6 ?m LDOF. We obtained process enhancement of 30% by using APSM. However, process instability is analyzed in a viewpoint of mask making and process issue such as mask fabrication capability, CD uniformity, and MEF. In simulation and experiment, 0.63NA ArF lithography shows resolution improvement compared to 0.70NA KrF. It is possible to obtain lOOnm pattern using ArF and APSM. Also, one of common issues is to reduce the MEF, which is decided by exposure and resist process condition. MEF is increased to about 4 or more in the sub-120nm range. This effect has influence on CD uniformity and EL margin. Reducing the MEF on the wafer, we have to optimize exposure tool, process, and mask. Shorter wavelength and APSM are one of candidates to minimize MEF. Therefore, ArF APSM is looking forward to high performance lithography.

With KrF and off-axis illumination (OAI) technique we should set up 150nm lithography process without using phase shift mask. But isolated-dense bias (ID bias) makes 150nm lithography process difficult. We investigated ID bias trend at different OAI condition and found that it could be reduced by optimizing OAI condition. We represent OAI as quadrupole center (sigma) R and pole size radius r. With high NA, small R and small r we can reduce ID bias but cannot eliminate completely at 150nm lithography. Also we found out that ID bias of duty patterns are more severe than that of dense and isolated patterns. Using OAI at a certain space width between lines, the width of lien has its minimum. This line thinning phenomena at this weak zone depends on OAI condition such as NA, R and coherence value. We compared simulation data with experimental result and could see the same phenomena at simulation data. Therefore OPC is necessary to avoid this weak zone. By experiment and simulation with NA higher than 0.65 and Optical Proximity Correction, we could set up 150nm lithography process with below 0.20micrometers periphery pattern design rule.

In order to develop 1 G bit DRAM of 0.18 micrometers design rule, it is required to generate 0.2 micrometers contact hole patterns with local DOF over 1.0 micrometers . One of good candidates is DUV attenuated phase shift mask (PSM), which improves the lithographic process margin such as depth of focus (DOF), especially in contact hole patterns due to edge enhancement effect. In the case of DUV attenuated PSM, the optimum condition for contact hole patterns near 0.2 micrometers has been investigated by simulations and experiments using chromium- based attenuated PSM with the transmittance of 6% at 248 nm wavelength. We obtained local DOF of 1.2 micrometers for 0.2 micrometers contact hole of 1 G bit DRAM with printing bias of -0.046 micrometers using KrF laser system (0.31 (sigma) , 0.55 NA). We evaluated the characteristics of contact hole with various duty ratios and defect printability using programmed defects.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

To extend the limitation of KrF lithography into the 110 nm design rule region, dipole off-axis illumination (OAI) is suggested. We have investigated the availability of the 1st-order efficiency as a method of optimization and confirmed it in the conventional OAI. By the 1st-order-efficiency method, we have designed two dipole apertures that are capable of resolving horizontal and vertical dense patterns, and have evaluated the basic performance of the modified dipole apertures. To verify the applicability of the modified dipole apertures to memory devices, we tested a variety of patterns and obtained fine patterns with the help of optical proximity correction (OPC). In this study, we found that the optimized dipole OAI can serve as an extension method of KrF lithography for 110 nm devices.