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In this paper, a CPW-fed antenna-in-package (AiP) operating at millimeter wave (mmWave) based on a wafer-level packaging technology with through silicon via (TSV) interconnections is proposed, designed, and measured. The designed antenna consists of two-stacked high-resistivity silicon (HRSi) substrates. One is the bottom HRSi substrate with thickness of 750 \mum, which carries the slot radiator and the CPW feeding. The other one is the top HRSi substrate with thickness of 200 \mum carrying a patch, which is placed on the radiating element for antenna gain and efficiency improvement. The vertical interconnects in this structure are designed using the TSVs built on a HRSi wafer, which are designed to carry the radio frequency (RF) signals up to mmWave. RF path transitions are carefully designed to minimize the return loss within 10 dB in the frequency band of concern. The designed AiP is fabricated and measured, and the measured results basically match the simulation results. It is demonstrated that a wider bandwidth and less-sensitive input impedance versus the fabrication process accuracy are obtained with the designed structure in this paper. The measured results show the radiation in the broadside of the structure with gain around 2.4 dBi from 76 to 93 GHz. [ABSTRACT FROM AUTHOR]

This paper presents the study on the effect of low-\kappa stacked layer, chip pad design structures, and shift pad design of a large die size Cu/low-\kappa chip for improving assembly and reliability performance on organic buildup substrate flip chip ball grid array (FCBGA). Bump shear characterization has been performed on the integrity of different stacked layer and pad structure, supported by bump shear modeling analysis. Initial reliability testing was performed on assembled package to identify the best choice of design and finally implemented on the reliability test vehicle for verification. In addition, a potential chip crack problem due to excessive warpage in FCBGA with large die assembly is examined and a simple failure criterion is proposed. [ABSTRACT FROM PUBLISHER]

Consumers' demands have driven the industry toward devices and packages with low cost, high performance, and multiple functions. Stacking two or more chips into one package becomes a popular choice. In this paper, the development of a three-die stack fine pitch ball grid array package is reported. A 65 nm Cu/low-k die is used as the bottom die in the package to increase the speed of the chip with multilayer interconnect structures. Compared to the conventional dielectrics, low-k materials are softer and less resistant to thermal-mechanical stress induced by packaging processes. In this paper, finite element analysis is performed to minimize the stress in low-k layers and to address the low-k delamination issue. In the dicing evaluation, comparison among straight cut, bevel cut and two-step cut was performed in terms of die strength and chipping results. It is found that the bevel cut dicing method is the best dicing method. The die attach process (especially wire embedded film process) is optimized to ensure that no voids are present in the die attach materials after the bonding process. The ultralow loop wire bonding process (50 \mum) is also well established. The maximum wire sweep for all test vehicles is less than 10% in the molding process. Finally, all samples for test vehicle 1 were shown to have successfully passed JEDEC component level tests such as thermal cycling for 1000 cycles (-40^\circC to 125^\circC) and high temperature storage (HTS at 150^\circC) for 1000 h. [ABSTRACT FROM PUBLISHER]