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An accurate and efficient algorithm is presented, which allows deriving the structure function of a discretized 3-D heat conduction problem. In this approach, the partial thermal conductances and capacitances in the structure function are computed in terms of weighted spatial averages of thermal resistivity and volumetric heat capacity. As a result, the exact influence of all materials and geometric details on each part of the structure function is determined. The approach is validated on a state-of-the-art SiGe heterojunction bipolar transistor (HBT) for high-frequency applications.

The development of efficient, cheap, compact, and reliable storage systems is getting increasingly crucial. Special attention must be given to Li Ion batteries, which stand out for the stability of their open circuit voltage (VOC), current capability, and compactness [1]. Such features make them suitable for a large scale of applications. Unfortunately, the design of electric/electronic systems embedding batteries as power supply/storage is still challenging because of the lack of simple and trustworthy circuital models accounting for complex thermo electrochemical mechanisms. In this abstract, a SPICE compatible compact electrical model of batteries including thermal and chemical effects (hereinafter referred to as macrocircuit) is proposed (Fig. 1). The macrocircuit was customized on a Li ion pouch cell battery in the NMC technology (schematically depicted in Fig. 2), its capacity being C=20 Ah; however, the model can be adapted to a generic product. First, in both the charge and discharge phases, self heating effects are considered along with their impact on the overall electrical behavior of the system. Furthermore, for each simulation, the initial conditions of the state of charge (SoC) of the battery can be defined; the SoC can be then monitored during the simulation run. The macrocircuit is composed by: (i) a core including a voltage generator VOC and a passive network, the values of which are allowed to vary with both the SoC and the cell average temperature (Tavg); (ii) a thermal feedback block (TFB) based on Foster I equivalent network, which provides Tavg as an output; (iii) some behavioral modeling blocks devoted to evaluate the SoC and the dissipated power (PD). It must be remarked that PD is given by the algebraic sum of two components, namely, the irreversible (PD,irr) and the reversible (PD,rev) one. While the former is always positive being it given by the Joule heating dissipation over the core, the latter accounts for the endothermic/exothermic chemical reactions dictated by the entropic coefficient dU/dT occurring in the battery; therefore, PD,rev can also be negative, thus reducing the overall PD and providing cooling effects. The modeling of the above quantities was based on the meticulous experimental campaign conducted in [2]. In order to prove the accuracy of the macrocircuit, simulative results obtained in the OrCAD SPICE software package [3] were compared with the counterpart performed in the FEM environment, which was used as a reference. The 3 D structure and the corresponding multiphysics FEM problem was (i) calibrated by means of the experimental data shown in [4], and simulations were run in COMSOL [5]. Given the initial state of charge SoC0=80% and Tamb=25°C, the discharge of the battery was emulated by defining an outgoing current at 4.5 C (i.e., 90 A). A good agreement between results carried out through the macrocircuit and FEM simulations was achieved in terms of dissipated power (Fig. 3), cell average temperature (Fig. 4), and voltage at the battery terminals (Fig. 5). It must be remarked that each FEM simulation required approximately 10 minutes, while a few seconds were needed by making use of the proposed model. As a further advantage, the model is prone to be adopted in complex SPICE simulations of circuits for applications in power electronics (such as DC/DC converters, inverters, and rectifiers) as well as to study the electrical connection of several pouch cells forming a battery pack.

This paper presents the modeling of the electrothermal and electromagnetic behavior in SiC-based multi-chip power modules. The proposed approach is based on a macromodeling technique and is applied to a realistic case-study. Preliminarily, the assembly under analysis was experimentally characterized to estimate its parasitics due to electromagnetic interactions. Extremely fast and efficient electrothermal simulations were then performed in a SPICE-like environment. Parasitics and nonlinear thermal effects were accounted for in simulations at high switching frequencies. Results demonstrate that such an approach can be successfully adopted in the design flow of power modules in any device technology.

In this paper, the dc electrothermal behavior of InGaP/GaAs HBT test devices and arrays for power amplifier output stages is extensively analyzed through an efficient simulation approach. The approach relies on a full circuit representation of the domains, which accounts for electrothermal effects through the thermal equivalent of the Ohm’s law and can be solved in any commercial circuit simulator. In particular, the power-temperature feedback is described through an equivalent thermal network automatically obtained by (i) generating a realistic 3-D geometry/mesh of the domain in the environment of a numerical tool with the aid of an in-house routine, (ii) feeding the geometry/mesh to FANTASTIC, which extracts the network without performing simulations. Nonlinear thermal effects adversely affecting the behavior of devices/arrays at high temperatures are included through a calibrated Kirchhoff’s transformation. For the test devices, the thermally-induced distortion in I–V curves is explained, and the limits of the safe operating regions are identified for a wide range of bias conditions. A deep insight into the electrothermal behavior of the arrays is then provided, with particular emphasis on the detrimental nonuniform operation. Useful guidelines are offered to designers in terms of layout and choice of the ballasting strategy.

In this paper, an advanced electrothermal simulation strategy is applied to a 3.3 kV silicon carbide MOSFET power module. The approach is based on a full circuital representation of the module, where use is made of the thermal equivalent of the Ohm’s law. The individual transistors are described with subcircuits, while the dynamic power-temperature feedback is accounted for through an equivalent thermal network enriched with controlled sources enabling nonlinear thermal effects. A synchronous step-up DC-DC converter and a single-phase inverter, both incorporating the aforementioned power module, are simulated. Good accuracy was ensured by considering electromagnetic effects due to parasitics, which were experimentally extracted in a preliminary stage. Low CPU times are needed, and no convergence issues are encountered in spite of the high switching frequencies. The impact of some key parameters is effortlessly quantified. The analysis witnesses the efficiency and versatility of the approach, and suggests its adoption for design, analysis, and synthesis of high-frequency power converters in wide-band-gap semiconductor technology.

This article focuses on the thermal analysis of direct bonded copper (DBC) substrates embedded in SiC-based multi-chip power modules. Due to the development of the innovative double-sided cooled technology, such substrates turn out to play a relevant and growing role in defining the PMs thermal, electrical, and mechanical performances. The study is aimed to compare typical ceramic materials adopted for the DBC manufacturing process; the comparison is carried out by means of exceptionally accurate nonlinear FEM 3-D simulations performed in the COMSOL Multiphysics environment. The influence of dissipated power and boundary conditions is thoroughly investigated by accounting for the temperature dependence of the thermal conductivities.

In this paper, an enriched version of a VHDL-AMS tool devoted to electro-thermo-mechanical simulations is presented. The major improvement consists in the evaluation of the vertical displacements of the layers in the domain. As a case study, the mechanical deformations and stress in a principle structure emulating a state-of-the-art multi-chip SiC-based power module are thoroughly examined. By means of the proposed approach, the vertical displacements were quickly investigated and quantified in a typical electro-thermo-mechanical stress test scenario.

This paper is aimed to investigate the electrical ruggedness of double-sided cooled power modules in SiC technology. In particular, an approach based on 3-D FEM simulations performed in the COMSOL Multiphysics environment is presented. In order to improve the module reliability and reduce the number of failure occurrences, most of the designers commonly adopt higher spacing among the interfacing DBC substrates that compose the assembly. The simulation results are devoted to meticulously quantify the beneficial effects of such spacing, thus providing useful guidelines for the design of power modules. An unexpected numerical outcome is then presented and a thorough explanation of the underlying physics is provided.

The relevant cooling action ensured by the thermal vias in PCB-based power circuits allows extending the operating conditions of the semiconductor devices. However, to properly drain off the power dissipated in the active regions, efficient thermal designs must be developed. To further reduce the devices operating temperature, a strategy to take advantage of the unexploited PCB areas surrounding the device footprint is proposed and discussed in this paper. The analysis is carried out by means of 3-D FEM thermal simulations performed in the COMSOL Multiphysics environment. This investigation is devoted to providing guidelines for an optimum design of thermal vias by accounting for their main geometrical features.

This article presents the detailed thermal analysis and modeling of multichip power modules (PMs). For the first time, a fair thermal comparison between the widespread single-sided cooled (SSC) technology and the innovative double-sided cooled (DSC) one is presented. The latter solution emerges among all packaging techniques due to its improved electrical performances and mechanical reliability. The investigation is carried out using 3-D finite-element method thermal simulations automated by an in-house routine. The PMs under test are thoroughly studied in a wide range of boundary conditions (BCs) in order to support the choice of an appropriate cooling strategy and the comprehension of the heat spreading (HS) effect occurring in such domains. In addition, attention is paid to dynamic behavior. Thermal modeling strategies are then proposed and discussed. As the main finding, no relevant thermal discrepancies were observed in the two PM technologies. In most of the BCs, the SSC PM enjoys an enhanced HS effect leading to a better thermal behavior with respect to the DSC counterpart, the adoption of which is justified only in the presence of excellent cooling systems.

This paper investigates the thermal vias (TVs) design in PCB-based power circuits; the study aims to experimentally validate an analytical model for the quick estimation of the TVs thermal resistance. Such a model efficiently supports the identification of the optimum PCB layout and allows avoiding time-demanding numerical simulations and/or nontrivial measurements. An experimental procedure performed on ad hoc PCB samples is exploited to confirm the model accuracy. The results of repeated measures and their statistical distribution are reported and discussed along with the model predictions.

This paper discusses the benefits of an advanced highly-efficient approach to static and dynamic electrothermal simulations of multicellular silicon carbide (SiC) power MOSFETs. The strategy is based on a fully circuital representation of the device, which is discretized into an assigned number of individual cells, high enough to analyze temperature and current nonuniformities over the active area. The cells are described with subcircuits implementing a simple transistor model that accounts for the utmost influence of the traps at the SiC/SiO2 interface. The power-temperature feedback is emulated with an equivalent network corresponding to a compact thermal model automatically generated by the FANTASTIC tool from an accurate 3D mesh of the component under test. The resulting macrocircuit can be solved by any SPICE-like simulation program with low computational burden and rare occurrence of convergence issues.